Computer networks
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis using path-based scheduling: algorithms and exercises
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A tree-based scheduling algorithm for control-dominated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Probability and Statistics with Reliability, Queuing and Computer Science Applications
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Formulation and evaluation of scheduling techniques for control flow graphs
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Glitch analysis and reduction in register transfer level power optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Register-transfer level estimation techniques for switching activity and power consumption
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Rapid performance estimation for system design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
DAC '98 Proceedings of the 35th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
A case study on modeling shared memory access effects during performance analysis of HW/SW systems
Proceedings of the 6th international workshop on Hardware/software codesign
Fast high-level power estimation for control-flow intensive design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Controller Resynthesis for Testability Enhancement of RTLController/Data Path Circuits
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Memory binding for performance optimization of control-flow intensive behaviors
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Fast performance analysis of bus-based system-on-chip communication architectures
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
IMPACT: a high-level synthesis system for low power control-flow intensive circuits
Proceedings of the conference on Design, automation and test in Europe
Performance analysis with confidence intervals for embedded software processes
Proceedings of the 14th international symposium on Systems synthesis
Control and communication performance analysis of embedded DSP systems in the MASIC methodology
Proceedings of the 14th international symposium on Systems synthesis
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A comprehensive high-level synthesis system for control-flow intensive behaviors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
PPS: a pipeline path-based scheduler
EDTC '95 Proceedings of the 1995 European conference on Design and Test
High-Level Synthesis with SIMD Units
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Leakage Power Analysis and Reduction during Behavioral Synthesis
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
High-level macro-modeling and estimation techniques for switching activity and power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis
Proceedings of the 41st annual Design Automation Conference
Memory binding for performance optimization of control-flow intensive behavioral descriptions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
Finding the best compromise in compiling compound loops to Verilog
Journal of Systems Architecture: the EUROMICRO Journal
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