High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
The Princeton University behavioral synthesis system
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Instruction-level parallel processing: history, overview, and perspective
The Journal of Supercomputing - Special issue on instruction-level parallelism
Performance analysis and optimization of schedules for conditional and loop-intensive specifications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Global scheduling for high-level synthesis applications
DAC '94 Proceedings of the 31st annual Design Automation Conference
Resource-Constrained Software Pipelining
IEEE Transactions on Parallel and Distributed Systems
Modulo scheduling of loops in control-intensive non-numeric programs
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Fast high-level power estimation for control-flow intensive design
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
IMPACT: a high-level synthesis system for low power control-flow intensive circuits
Proceedings of the conference on Design, automation and test in Europe
Transient power management through high level synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Time-constrained scheduling of large pipelined datapaths
Journal of Systems Architecture: the EUROMICRO Journal
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Finding the best compromise in compiling compound loops to Verilog
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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In this paper, we present a novel scheduling algorithm targeted towards minimizing the average execution time of control-flow intensive behavioral descriptions. Our algorithm uses a CDFG model, which preserves the parallelism inherent in the application. It explores previously unexplored regions of the solution space by its ability to overlap the schedules of independent iterative constructs, whose bodies share resources. It also incorporates well known optimization techniques like loop unrolling in a natural fashion. This is made possible by a general loop-handling technique, which we have devised. Application of the algorithm to several common benchmarks demonstrates up to 4.8-fold improvement in expected schedule length over existing scheduling algorithms, without paying a price in terms of the best- and worst-case schedule lengths required to execute the behavioral description (in fact, frequently, the best/worst-case schedule lengths are also better for our algorithm).