Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Exploiting state equivalence on the fly while applying code motion and speculation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Behavioral network graph: unifying the domains of high-level and logic synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A reordering technique for efficient code motion
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A code-motion pruning technique for global scheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IMPACT: a high-level synthesis system for low power control-flow intensive circuits
Proceedings of the conference on Design, automation and test in Europe
An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A comprehensive high-level synthesis system for control-flow intensive behaviors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Microprocessors & Microsystems
A low-power scheduling tool for system on a chip designs
WSEAS Transactions on Circuits and Systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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As high-level synthesis techniques gain acceptance among designers, it is important to be able to provide a robust system which can handle large designs in short execution times, producing high-quality results. Scheduling is one of the most complex tasks in high-level synthesis, and although many algorithms exist for solving the scheduling problem, it remains a main source of inefficiency by either not producing high-quality results, not taking into account realistic design requirements, or requiring unacceptable execution times. One of the main problems in scheduling is the dichotomy between control and data. Many algorithms to date have been able to provide scheduling solutions by looking only at either the data part or the control part of the design. This has been done in order to simplify the problem; however, it has resulted in many algorithms unable to handle efficiently large designs with complex control and data functionality. This paper presents algorithms for combining dataflow and control-flow techniques into a robust scheduling system. The main characteristics of this system are as follows: 1) it uses path-based techniques for efficient handling of control and mutual exclusiveness (for resource sharing), 2) it allows operation reordering and parallelism extraction within the context of path-based scheduling, 3) it contains a control partitioning algorithm for design space exploration as well as for reducing the number of control paths, and 4) it combines the above algorithms into an adaptive scheduling system which is capable of trading optimality for execution time on-the-fly. Results involving billions of paths are presented and analyzed.