Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Allocation algorithms based on path analysis
Integration, the VLSI Journal - Special issue on high-level synthesis
An efficient algorithm for Microword length minimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Condition graphs for high-quality behavioral synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Incorporating speculative execution in exact control-dependent scheduling
DAC '94 Proceedings of the 31st annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
False path analysis based on hierarchical control representation
Proceedings of the 11th international symposium on System synthesis
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An algorithm to determine mutually exclusive operations in behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Analysis of conditional resource sharing using a guard-based control representation
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A unified scheduling model for high-level synthesis and code generation
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Hierarchical Conditional Dependency Graphs for Mutual Exclusiveness Identification
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Hierarchical Conditional Dependency Graphs for Conditional Resource Sharing
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Constraints-driven scheduling and resource assignment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Systematic preprocessing of data dependent constructs for embedded systems
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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In high-level hardware synthesis (HLS) there is a gap on the quality of the synthesized results between data-flow and control-flow dominated behavioral descriptions. Heuristics destined for the former usually perform poorly on the latter. To close this gap, the CODESIS interactive HLS tool relies on a unifying intermediate design representation and adapted heuristics that are able to accommodate both types of designs as well as designs of a mixed data-flow and control-flow nature. Preliminary experimental results in mutual exclusiveness detection and in efficiently scheduling conditional behaviors, are encouraging and prompt for more extensive experimentation.