Analysis of conditional resource sharing using a guard-based control representation

Authors:
Ivan P. Radivojevic;Forrest Brewer
Affiliations:
-;-
Venue:
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Year:
1995

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Abstract

Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of throughput is desired. In this paper, an exact and efficient conditional resource sharing analysis using a guardbased control representation is presented. The analysis is transparent to a scheduler implementation. The proposed technique systematically handles complex conditional resource sharing for cases when folded (software pipelined) loops include conditional behavior within the loop body.