An efficient method of computing static single assignment form
POPL '89 Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
The hierarchical task graph and its use in auto-scheduling
ICS '91 Proceedings of the 5th international conference on Supercomputing
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Representing conditional branches for high-level synthesis applications
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Allocation algorithms based on path analysis
Integration, the VLSI Journal - Special issue on high-level synthesis
An efficient algorithm for Microword length minimization
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A tree-based scheduling algorithm for control-dominated circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Condition graphs for high-quality behavioral synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Bridge: a versatile behavioral synthesis system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A code-motion pruning technique for global scheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An algorithm to determine mutually exclusive operations in behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
High-level synthesis using hierarchical conditional dependency graphs in the CODESIS system
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Automatic Extraction of Functional Parallelism from Ordinary Programs
IEEE Transactions on Parallel and Distributed Systems
Analysis of conditional resource sharing using a guard-based control representation
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A unified scheduling model for high-level synthesis and code generation
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Translation of Statecharts into Signal Approach of Time, Interoperability
CSD '98 Proceedings of the 1998 International Conference on Application of Concurrency to System Design
Predicated Static Single Assignment
PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
Hierarchical Conditional Dependency Graphs for Mutual Exclusiveness Identification
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Percolation Scheduling: A Parallel Compilation Technique
Percolation Scheduling: A Parallel Compilation Technique
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Timed decision table and its applications in pre-synthesis and partial synthesis of digital circuits
Timed decision table and its applications in pre-synthesis and partial synthesis of digital circuits
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Wavesched: a novel scheduling technique for control-flow intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incorporating speculative execution into scheduling of control-flow-intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Software thread integration for embedded system display applications
ACM Transactions on Embedded Computing Systems (TECS)
Area optimization of multi-cycle operators in high-level synthesis
Proceedings of the conference on Design, automation and test in Europe
Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Performance-driven scheduling of behavioural specifications
Integration, the VLSI Journal
Constraint-Driven Identification of Application Specific Instructions in the DURASE System
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Clock-driven distributed real-time implementation of endochronous synchronous programs
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Scheduling with soft constraints
Proceedings of the 2009 International Conference on Computer-Aided Design
Finding the best compromise in compiling compound loops to Verilog
Journal of Systems Architecture: the EUROMICRO Journal
Timing variation-aware scheduling and resource binding in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Runtime dependency analysis for loop pipelining in high-level synthesis
Proceedings of the 50th Annual Design Automation Conference
Modeling and simulation in a formal design framework
Proceedings of the 6th Balkan Conference in Informatics
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As hardware designs get increasingly complex and time-to-market constraints get tighter there is strong motivation for high-level synthesis (HLS). HLS must efficiently handle both dataflow-dominated and controlflow-dominated designs as well as designs of a mixed nature. In the past efficient tools for the former type have been developed but so far HLS of conditional behaviors lags behind. To bridge this gap an efficient scheduling heuristic for conditional behaviors is presented. Our heuristic and the techniques it utilizes are based on a unifying design representation appropriate for both types of behavioral descriptions, enabling the proposed heuristic to exploit under the same framework several well-established techniques (chaining, multicycling) as well as conditional resource sharing and speculative execution which are essential in efficiently scheduling conditional behaviors. Preliminary experiments confirm the effectiveness of our approach and prompted the development of the CODESIS HLS tool for further experimentation.