Compiler design in C
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
SUIF: an infrastructure for research on parallelizing and optimizing compilers
ACM SIGPLAN Notices
C-based synthesis experiences with a behavior synthesizer, “cyber”
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Synthesis of hardware models in C with pointers and complex data structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Logic, Programming, and PROLOG
Logic, Programming, and PROLOG
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Introduction to the Scheduling Problem
IEEE Design & Test
A comprehensive high-level synthesis system for control-flow intensive behaviors
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
High-level Synthesis of Multi-process Behavioral Descriptions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental exploration of the combined physical and behavioral design space
Proceedings of the 42nd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, a formal design framework is described that it allows for correct-by-construction complex circuit generation from high-level program models with arbitrary data and control flow. The formal nature of the program compilation allows for design flow iteration -- free design, rapid development times and bug-free product implementation. The discussed formal framework, translates program subroutines into hardware coprocessors. The translation process is implemented with formal compiler-compiler and logic programming techniques. Due to this the functionality of the generated finite-state-machines and datapaths is formally equivalent to that of the source programs. This is practically proven in this paper with verification of the designed systems at both the program code and at the produced circuit RTL simulations level. The presented design flow enables rapid prototyping and it allows for compression of the development time from months down to a few hours.