Integer and combinatorial optimization
Integer and combinatorial optimization
Optimal scheduling and allocation of embedded VLSI chips
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Algorithms for High-Level Synthesis
IEEE Design & Test
Introduction to High-Level Synthesis
IEEE Design & Test
From VHDL to efficient and first-time-right designs: a formal approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Behavioral synthesis with systemC
Proceedings of the conference on Design, automation and test in Europe
Design Methodology for a Large Communication Chip
IEEE Design & Test
Refinement and Property Checking in High-Level Synthesis using Attribute Grammars
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Verification of Basic Block Schedules Using RTL Transformations
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Scheduling under resource constraints using dis-equations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Triage: balancing energy and quality of service in a microserver
Proceedings of the 5th international conference on Mobile systems, applications and services
Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Finding the best compromise in compiling compound loops to Verilog
Journal of Systems Architecture: the EUROMICRO Journal
Using speculative functional units in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
A pattern selection algorithm for multi-pattern scheduling
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
CLASSY: a clock analysis system for rapid prototyping of embedded applications on MPSoCs
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
Run-time generation of partial FPGA configurations for subword operations
Microprocessors & Microsystems
Modeling and simulation in a formal design framework
Proceedings of the 6th Balkan Conference in Informatics
Compiling for power with ScalaPipe
Journal of Systems Architecture: the EUROMICRO Journal
Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The benefits of using variable-length pipelined operations in high-level synthesis
ACM Transactions on Embedded Computing Systems (TECS)
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The scheduling problem one of the central tasks in high-level synthesis is the problem of determining the order in which the operations in the behavioral description will execute. This tutorial introduces the scheduling problem and describes four scheduling algorithms commonly used today to solve those problems.