Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
Introduction to the Scheduling Problem
IEEE Design & Test
Combined Formal Post- and Presynthesis Verification in High Level Synthesis
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
ICCD '98 Proceedings of the International Conference on Computer Design
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Formal verification of code motion techniques using data-flow-driven equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Translation validation of scheduling in high level synthesis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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We present an approach to aid in debugging/development ofsc heduling algorithm implementations. Our technique makes use ofa sequence ofa correctness-preserving RTL transformation called Register Transfer Split (RTS), to collectively perform the same task as that of a scheduler. Violation ofthe transformation precondition signals an error and the sequence of RTS transformations applied so far forms a trace which can be used for debugging purposes.