Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Global scheduling with code-motions for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A reordering technique for efficient code motion
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Verification of embedded systems using a petri net based representation
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Influence of compiler optimizations on system power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Verification of Basic Block Schedules Using RTL Transformations
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An evaluation of code and data optimizations in the context of disk power reduction
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Reducing energy consumption of multiprocessor SoC architectures by exploiting memory bank locality
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hand-in-hand verification of high-level synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Validating High-Level Synthesis
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Verified validation of lazy code motion
Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Incorporating speculative execution into scheduling of control-flow-intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using global code motions to improve the quality of results for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Behavioural equivalence checking of the refinements of the input behaviours taking place at various phases of synthesis of embedded systems or VLSI circuits is a well pursued field. Although extensive literature on equivalence checking of sequential behaviours exists, similar treatments for parallel behaviours are rare mainly because of all the possible execution scenarios inherent in them. Here, we propose a translation algorithm from a parallel behaviour, represented by an untimed PRES+ model, to a sequential behaviour, represented by an FSMD model. Several equivalence checkers for FSMD models already exist for various code based transformation techniques. We have satisfactorily performed equivalence checking of some high level synthesis benchmarks represented by untimed PRES+ models by first translating them into FSMD models using our algorithm and subsequently feeding them to one such FSMD equivalence checker.