A Formal Verification Method of Scheduling in High-level Synthesis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Hand-in-hand verification of high-level synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Validating High-Level Synthesis
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Proceedings of the 16th Asia and South Pacific Design Automation Conference
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VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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This paper presents a methodology for the formal verification of scheduling during High-Level Synthesis(HLS). A notion of functional equivalence between two Finite State Machines with Datapath (FSMDs) is de.ned, on the basis of which we propose a methodology to verify scheduling. The functional equivalence between the behavioral specification and the scheduled Control-Data Flow Graph (CDFG) - that is the result of scheduling - is established using their FSMD models. The equivalence conditions are mathematically modeled and implemented in the higher-order specification language of theorem proving environment PVS [11], integrated with a HLS tool. The proof of correctness of the design is subsequently verified by the PVS proof checker.