Global scheduling with code-motions for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
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ISSS '97 Proceedings of the 10th international symposium on System synthesis
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A reordering technique for efficient code motion
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 27th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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DATE '00 Proceedings of the conference on Design, automation and test in Europe
Dynamic common sub-expression elimination during scheduling in high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
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CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
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HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
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PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Optimizing for space and time usage with speculative partial redundancy elimination
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification method of dataflow algorithms in high-level synthesis
Journal of Systems and Software
Model Checking Software at Compile Time
TASE '07 Proceedings of the First Joint IEEE/IFIP Symposium on Theoretical Aspects of Software Engineering
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
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CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Automatic Bug Detection in Microcontroller Software by Static Program Analysis
SOFSEM '09 Proceedings of the 35th Conference on Current Trends in Theory and Practice of Computer Science
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FMICS'07 Proceedings of the 12th international conference on Formal methods for industrial critical systems
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Translation validation of high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
An incremental and layered procedure for the satisfiability of linear arithmetic logic
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Incorporating speculative execution into scheduling of control-flow-intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using global code motions to improve the quality of results for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A formal verification method for checking correctness of code motion techniques is presented in this article. Finite State Machine with Datapath (FSMD) models have been used to represent the input and the output behaviors of each synthesis step. The method introduces cutpoints in one FSMD, visualizes its computations as concatenation of paths from cutpoints to cutpoints, and then identifies equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. Unlike many other reported techniques, the method is capable of verifying both uniform and nonuniform code motion techniques. It has been underlined in this work that for nonuniform code motions, identifying equivalent path segments involves model checking of some data-flow properties. Our method automatically identifies the situations where such properties are needed to be checked during equivalence checking, generates the appropriate properties, and invokes the model checking tool NuSMV to verify them. The correctness and the complexity of the method have been dealt with. Experimental results demonstrate the effectiveness of the method.