Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Redundant operator creation: a scheduling optimization technique
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Critical path minimization using retiming and algebraic speed-up
DAC '93 Proceedings of the 30th international Design Automation Conference
A new framework for exhaustive and incremental data flow analysis using DJ graphs
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
Incremental computation of dominator trees
ACM Transactions on Programming Languages and Systems (TOPLAS)
A specification invariant technique for operation cost minimisation in flow-graphs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Advanced compiler design and implementation
Advanced compiler design and implementation
Maximally fast and arbitrarily fast implementation of linear computations
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A reordering technique for efficient code motion
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A global resource-constrained parallelization technique
ICS '89 Proceedings of the 3rd international conference on Supercomputing
Partial redundancy elimination in SSA form
ACM Transactions on Programming Languages and Systems (TOPLAS)
Analysis of high-level address code transformations for programmable processors
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Speculation techniques for high level synthesis of control intensive designs
Proceedings of the 38th annual Design Automation Conference
Conditional speculation and its effects on performance and area for high-level snthesis
Proceedings of the 14th international symposium on Systems synthesis
Mutation Scheduling: A Unified Approach to Compiling for Fine-Grain Parallelism
LCPC '94 Proceedings of the 7th International Workshop on Languages and Compilers for Parallel Computing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new algorithm for elimination of common subexpressions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of data-flow computations using canonical TED representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing data-flow graphs with min/max, adding and relational operations
Proceedings of the Conference on Design, Automation and Test in Europe
Optimizing data flow graphs to minimize hardware implementation
Proceedings of the Conference on Design, Automation and Test in Europe
Formal verification of code motion techniques using data-flow-driven equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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We introduce a new approach, "Dynamic Common Sub-expression Elimination (CSE)", that dynamically eliminates common sub- expressions based on new opportunities created during scheduling of control-intensive designs. Classical CSE techniques fail to eliminate several common sub-expressions in control-intensive designs due to the presence of a complex mix of control and data-flow. Aggressive speculative code motions employed to schedule control-intensive designs often re-order, speculate and duplicate operations, hence changing the control flow between the operations with common sub-expressions. This leads to new opportunities for applying CSE dynamically. We have implemented dynamic CSE in a high-level synthesis framework called Spark and present results for experiments performed using various combinations of CSE and dynamic CSE. The benchmarks used consist of four functional blocks derived from two moderately complex industrial-strength applications, namely, MPEG-1 and the GIMP image processing tool. Our dynamic CSE techniques result in improvements of up to 22% in the controller size and up to 31% in performance; easily surpassing the improvements obtained by the traditional CSE approach. We also observe an unexpected (and significant) reduction in the number of registers using our approach.