Optimization of data-flow computations using canonical TED representation

Authors:
Maciej Ciesielski;Daniel Gomez-Prado;Qian Ren;Jérémie Guillot;Emmanuel Boutillon
Affiliations:
Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA;VLSI CAD Laboratory, Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA;Synopsys, Inc., Mountain View, CA;Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Montpellier, France;Laboratoire des Sciences et Techniques de l'Information de la Communication et de la Connaissance, Université de Bretagne Sud, Lorient, France
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

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Abstract

An efficient graph-based method to optimize polynomial expressions in data-flow computations is presented. The method is based on the factorization, common-subexpression elimination, and decomposition of algebraic expressions performed on a canonical Taylor expansion diagram representation. It targets the minimization of the latency and hardware cost of arithmetic operators in the scheduled implementation. The generated data-flow graphs are better suited for high-level synthesis than those extracted directly from the initial specification or obtained with traditional algebraic decomposition methods. Experimental results show that the resulting implementations are characterized by better performance and smaller datapath area than those obtained using traditional algebraic decomposition techniques. The described method is generic, applicable to arbitrary algebraic expressions, and does not require any knowledge of the application domain.