Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Schema polynomials and applications
EDBT '08 Proceedings of the 11th international conference on Extending database technology: Advances in database technology
Polynomial datapath optimization using partitioning and compensation heuristics
Proceedings of the 46th Annual Design Automation Conference
Optimization of data-flow computations using canonical TED representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improved heuristics for finite word-length polynomial datapath optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs
International Journal of Reconfigurable Computing
Modular datapath optimization and verification based on modular-HED
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing data flow graphs to minimize hardware implementation
Proceedings of the Conference on Design, Automation and Test in Europe
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits
Proceedings of the International Conference on Computer-Aided Design
Polynomial datapath optimization using constraint solving and formal modelling
Proceedings of the International Conference on Computer-Aided Design
Optimized code generation for finite element local assembly using symbolic manipulation
ACM Transactions on Mathematical Software (TOMS)
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Polynomial expressions are frequently encountered in many application domains, particularly in signal processing and computer graphics. Conventional compiler techniques for redundancy elimination such as common subexpression elimination (CSE) are not suited for manipulating polynomial expressions, and designers often resort to hand optimizing these expressions. This paper leverages the algebraic techniques originally developed for multilevel logic synthesis to optimize polynomial expressions by factoring and eliminating common subexpressions. The proposed algorithm was tested on a set of benchmark polynomial expressions where savings of 26.7% in latency and 26.4% in energy consumption were observed for computing these expressions on the StrongARM SA1100 processor core. When these expressions were synthesized in custom hardware, average energy savings of 63.4% for minimum hardware constraints and 24.6% for medium hardware constraints over CSE were observed