Code Generation for Expressions with Common Subexpressions
Journal of the ACM (JACM)
Generation of optimal code for expressions via factorization
Communications of the ACM
Factoring and eliminating common subexpressions in polynomial expressions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimization of polynomial datapaths using finite ring algebra
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Approximate factorization of multivariate polynomials using singular value decomposition
Journal of Symbolic Computation
Polynomial datapath optimization using partitioning and compensation heuristics
Proceedings of the 46th Annual Design Automation Conference
Application of symbolic computer algebra in high-level data-flow synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modular datapath optimization and verification based on modular-HED
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Polynomial datapath optimization using constraint solving and formal modelling
Proceedings of the International Conference on Computer-Aided Design
Microprocessors & Microsystems
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Conventional high-level synthesis techniques are not able to manipulate polynomial expressions efficiently due to the lack of suitable optimization techniques for redundancy elimination over Z2n. This paper, in comparison with [1], presents 1) an improved partitioning heuristic based on single-variable monomials instead of checking all sub-polynomials, 2) an improved compensation heuristic which is able to compensate monomials as well as coefficients, and 3) a combined area-delay-optimized factorization approach to extract the most frequently used sub-expressions from multi-output polynomials over Z2n. Experimental results have shown an average saving of 32% and 27.2% in the number of logic gates and critical path delay respectively compared to the state-of-the-art techniques. Regarding the comparison with [1], the number of gates and delay are improved by 14.3% and 13.9% respectively. Furthermore, the results show that the combined area-delay optimization can reduce the average delay by 26.4%.