Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Transformation and synthesis of FSMs for low-power gated-clock implementation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
An exact methodology for scheduling in a 3D design space
ISSS '95 Proceedings of the 8th international symposium on System synthesis
LOT: logic optimization with testability—new transformations using recursive learning
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HDL optimization using timed decision tables
DAC '96 Proceedings of the 33rd annual Design Automation Conference
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A new method towards achieving global optimality in technology mapping
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
VERILAT: verification using logic augmentation and transformations
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A reconfigurable hardware approach to network simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Metamorphosis: state assignment by retiming and re-encoding
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Power analysis for sequential circuits at logic level
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Storage optimization by replacing some flip-flops with latches
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Assignment of storage values to sequential read-write memories
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Module assignment for low power
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A high-level synthesis approach to optimum design of self-checking circuits
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Gate-level synthesis for low-power using new transformations
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Determining the Order of Processor Transactions in StaticallyScheduled Multiprocessors
Journal of VLSI Signal Processing Systems
Low power high level synthesis by increasing data correlation
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Re-mapping for low power under tight timing constraints
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
A survey of Boolean matching techniques for library binding
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Datapath scheduling with multiple supply voltages and level converters
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An improved algorithm for minimum-area retiming
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimizing designs containing black boxes
DAC '97 Proceedings of the 34th annual Design Automation Conference
Exact coloring of real-life graphs is easy
DAC '97 Proceedings of the 34th annual Design Automation Conference
System level fixed-point design based on an interpolative approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
Synthesis of application specific programmable processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Profile-driven program synthesis for evaluation of system power dissipation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generalized matching from theory to application
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Decomposition of timed decision tables and its use in presynthesis optimizations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
High-level area and power estimation for VLSI circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Decomposition and technology mapping of speed-independent circuits using Boolean relations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
High-level scheduling model and control synthesis for a broad range of design applications
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
OPTIMIST: state minimization for optimal 2-level logic implementation
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Maximum independent sets on transitive graphs and their applications in testing and CAD
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Physical design: mathematical models and methods
Proceedings of the 1997 international symposium on Physical design
The future of logic synthesis and physical design in deep-submicron process geometries
Proceedings of the 1997 international symposium on Physical design
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Partitioning sequential circuits on dynamically reconfiguable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
M32: a constructive multilevel logic synthesis system
DAC '98 Proceedings of the 35th annual Design Automation Conference
Efficient Boolean division and substitution
DAC '98 Proceedings of the 35th annual Design Automation Conference
Delay estimation VLSI circuits from a high-level view
DAC '98 Proceedings of the 35th annual Design Automation Conference
A reconfigurable logic machine for fast event-driven simulation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Technology mapping for large complex PLDs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Parallel compiled event driven VHDL simulation
ICS '98 Proceedings of the 12th international conference on Supercomputing
Intellectual property protection by watermarking combinational logic synthesis solutions
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Reencoding for cycle-time minimization under fixed encoding length
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A general approach for regularity extraction in datapath circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A new algorithm for the reduction of incompletely specified finite state machines
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Concurrent error detection at architectural level
Proceedings of the 11th international symposium on System synthesis
Fine grain incremental rescheduling via architectural retiming
Proceedings of the 11th international symposium on System synthesis
Rate analysis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Two-level logic minimization for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Resource constrained dataflow retiming heuristics for VLIW ASIPs
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Overhead effects in real-time preemptive schedules
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Allocation Techniques for Reducing BIST Area Overhead ofData Paths
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
IEEE Transactions on Computers
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Exploiting state equivalence on the fly while applying code motion and speculation
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Performance driven resynthesis by exploiting retiming-induced state register equivalence
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Engineering change: methodology and applications to behavioral and system synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On ILP formulations for built-in self-testable data path synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Behavioral synthesis techniques for intellectual property protection
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Lower and upper bounds on the switching activity in scheduled data flow graphs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Efficient switching activity computation during high-level synthesis of control-dominated designs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
A Note on the Polynomial Form of Boolean Functions and Related Topics
IEEE Transactions on Computers
Web-based analysis and distributed IP
Proceedings of the 31st conference on Winter simulation: Simulation---a bridge to the future - Volume 2
A code-motion pruning technique for global scheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
IEEE Transactions on Computers
Efficient algorithms for acceptable design exploration
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Behavioral-level partitioning for low power design in control-dominated application
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Technology Road Map to Methodologies for Mixed-Signal System Designand Simulation
Journal of VLSI Signal Processing Systems - Mixed-signal design issues
Technology Road Map to Methodologies for Mixed-Signal System Design& Simulation
Analog Integrated Circuits and Signal Processing - Special issue on mixed-signal design issues
Heuristic tradeoffs between latency and energy consumption in register assignment
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Hierarchical Test Generation Approach for Large Controllers
IEEE Transactions on Computers
Least Upper Bounds for the Size of OBDDs Using Symmetry Properties
IEEE Transactions on Computers
Macro-driven circuit design methodology for high-performance datapaths
Proceedings of the 37th Annual Design Automation Conference
A bipartition-codec architecture to reduce power in pipelined circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Lower bound on latency for VLIW ASIP datapaths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Localized watermarking: methodology and application to operation scheduling
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
DG2VHDL: A Tool to Facilitate the High Level Synthesisof Parallel Processing Array Architectures
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Technology mapping and retargeting for field-programmable analog arrays
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On using satisfiability-based pruning techniques in covering algorithms
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Application of Reconfigurable CORDIC Architectures
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Synthesis of low-power selectively-clocked systems from high-level specification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient optimal design space characterization methodologies
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Retiming-based factorization for sequential logic optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware/software synthesis of formal specifications in codesign of embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
IEEE Transactions on Computers
Performance-driven mapping for CPLD architectures
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Formal Methods in System Design
Behavioral synthesis with systemC
Proceedings of the conference on Design, automation and test in Europe
On applying the set covering model to reseeding
Proceedings of the conference on Design, automation and test in Europe
On-the-fly layout generation for PTL macrocells
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the conference on Design, automation and test in Europe
Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers
Proceedings of the conference on Design, automation and test in Europe
Static memory allocation by pointer analysis and coloring
Proceedings of the conference on Design, automation and test in Europe
Heuristic datapath allocation for multiple wordlength systems
Proceedings of the conference on Design, automation and test in Europe
Hardware/software partitioning with integrated hardware design space exploration
Proceedings of the conference on Design, automation and test in Europe
Scheduling and module assignment for reducing BIST resources
Proceedings of the conference on Design, automation and test in Europe
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Verification by simulation comparison using interface synthesi
Proceedings of the conference on Design, automation and test in Europe
An algorithm to determine mutually exclusive operations in behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
A new paradigm for dichotomy-based constrained encoding
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
IEEE Transactions on Computers
Designing domain-specific processors
Proceedings of the ninth international symposium on Hardware/software codesign
A novel parallel deadlock detection algorithm and architecture
Proceedings of the ninth international symposium on Hardware/software codesign
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Semiconcurrent Error Detection in Data Paths
IEEE Transactions on Computers
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Transformations for the synthesis and optimization of asynchronous distributed control
Proceedings of the 38th annual Design Automation Conference
Using symbolic algebra in algorithmic level DSP synthesis
Proceedings of the 38th annual Design Automation Conference
A new structural pattern matching algorithm for technology mapping
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
Statistical design space exploration for application-specific unit synthesis
Proceedings of the 38th annual Design Automation Conference
Input space adaptive design: a high-level methodology for energy and performance optimization
Proceedings of the 38th annual Design Automation Conference
Low power pipelining of linear systems: a common operand centric approach
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Introducing redundant computations in RTL data paths for reducing BIST resources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Lower bound estimation for low power high-level synthesis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
A fast approach to computing exact solutions to the resource-constrained scheduling problem
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimal design of synchronous circuits using software pipelining techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing resources in a repeating schedule for a split-node data-flow graph
Proceedings of the 12th ACM Great Lakes symposium on VLSI
IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
A low power scheduling scheme with resources operating at multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral synthesis via engineering change
Proceedings of the 39th annual Design Automation Conference
Handling special constructs in symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Forward-looking objective functions: concept & applications in high level synthesis
Proceedings of the 39th annual Design Automation Conference
Technology mapping algorithms for domino logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic Synthesis and Verification
Logic Synthesis and Verification
Logic Synthesis and Verification
Logic Synthesis and Verification
Optimization of synchronous circuits
Logic Synthesis and Verification
Logic Synthesis and Verification
Readings in hardware/software co-design
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Rate analysis for embedded systems
Readings in hardware/software co-design
Readings in hardware/software co-design
Lower bound on latency for VLIW ASIP datapaths
Readings in hardware/software co-design
Cluster assignment for high-performance embedded VLIW processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal Methods in System Design
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Hardware implementation of intelligent systems
Exploring performance tradeoffs for clustered VLIW ASIPs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Improving memory energy using access pattern classification
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Symbolic algebra and timing driven data-flow synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A system for synthesizing optimized FPGA hardware from MATLAB
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Behavior-to-placed RTL synthesis with performance-driven placement
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The sizing rules method for analog integrated circuit design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Hardware-Software partitioning and pipelined scheduling of transformative applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BDD-based logic synthesis for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Structural Fault Testing of Embedded Cores Using Pipelining
Journal of Electronic Testing: Theory and Applications
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
IEEE Design & Test
Introduction to High-Level Synthesis
IEEE Design & Test
Specification and Design of Embedded Hardware-Software Systems
IEEE Design & Test
Fault Analysis for Networks with Concurrent Error Detection
IEEE Design & Test
A Methodology for Synthesis of Data Path Circuitse
IEEE Design & Test
Computer-Aided Hardware-Software Codesign
IEEE Micro
Automatic Parallelization of Compiled Event Driven VHDL Simulation
IEEE Transactions on Computers
Global memory mapping for FPGA-based reconfigurable systems
IPDPS '01 Proceedings of the 15th International Parallel & Distributed Processing Symposium
Improving Offset Assignment for Embedded Processors
LCPC '00 Proceedings of the 13th International Workshop on Languages and Compilers for Parallel Computing-Revised Papers
A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs
IWDC '02 Proceedings of the 4th International Workshop on Distributed Computing, Mobile and Wireless Computing
An A-Prolog Decision Support System for the Space Shuttle
PADL '01 Proceedings of the Third International Symposium on Practical Aspects of Declarative Languages
Functional Design Using Behavioural and Structural Components
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Flexibility/Cost-Tradeoffs of Platform-Based Systems
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
Verification of Basic Block Schedules Using RTL Transformations
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Embedded Software in Network Processors - Models and Algorithms
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Value Prediction in Engineering Applications
Proceedings of the 14th International conference on Industrial and engineering applications of artificial intelligence and expert systems: engineering of intelligent systems
Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Multiple-Wordlength Resource Binding
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Fast Prototyping with Co-operation of Simulation and Emulation
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
An Algorithm for Recruitment of Agents in Agency Design
AI*IA '99 Proceedings of the 6th Congress of the Italian Association for Artificial Intelligence on Advances in Artificial Intelligence
Hardware Synthesis Using SAFL and Application to Processor Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
SAS '01 Proceedings of the 8th International Symposium on Static Analysis
Flexibility/cost-tradeoffs of platform-based systems
Embedded processor design challenges
High-level synthesis of distributed logic-memory architectures
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Synthesis of custom processors based on extensible platforms
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
FPGA resource and timing estimation from Matlab execution traces
Proceedings of the tenth international symposium on Hardware/software codesign
Design and synthesis of dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Journal of Systems Architecture: the EUROMICRO Journal
Systems Analysis Modelling Simulation
Algorithm and architecture-level design space exploration using hierarchical data flows
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
ADPCM codec: from system level description to versatile HDL model
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
From STG to Extended-Burst-Mode Machines
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
On the Existence of Hazard-Free Multi-Level Logic
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Synthesis of saturation arithmetic architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design for Testability of Gated-Clock FSMs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Solving Graph Optimization Problems with ZBDDs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Adaptive least mean square behavioral power modeling
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An evolutionary approach to system-level synthesis
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
Critical path driven cosynthesis for heterogeneous target architectures
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Instance-Specific Accelerators for Minimum Covering
The Journal of Supercomputing
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Retiming with logic duplication transformation: theory and an application to partial scan
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Synchronous Controller Models for Synthesis from Communicating VHDL Processes
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Synthesis for Logical Initializability of Synchronous Finite State Machines
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
High-level Synthesis of Multi-process Behavioral Descriptions
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A high-level synthesis approach to design of fault-tolerant systems
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
1.3 Parallelism in Structural Fault Testing of Embedded Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
COMBINATIONAL LOGIC SYNTHESIS FOR DIVERSITY IN DUPLEX SYSTEMS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
SCAN SYNTHESIS FOR ONE-HOT SIGNALS
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Efficient Place and Route for Pipeline Reconfigurable Architectures
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Symbolic Binding for Clustered VLIW ASIPs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Synthesis of low-power selectively-clocked systems from high-level specification
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Toward a Practical Methodology for Completely Characterizing the Optimal Design Space
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Mapping of generalized template matching onto reconfigurable computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Effective and efficient FPGA synthesis through general functional decomposition
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
A BIST Pattern Generator Design for Near-Perfect Fault Coverage
IEEE Transactions on Computers
Satisfiability-Based Algorithms for Boolean Optimization
Annals of Mathematics and Artificial Intelligence
A Range-Compaction Heuristic for Graph Coloring
Journal of Heuristics
Application-specific instruction generation for configurable processor architectures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Crosstalk Minimization in Logic Synthesis for PLA
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Access Pattern Restructuring for Memory Energy
IEEE Transactions on Parallel and Distributed Systems
A decomposition procedure for register-transfer level power management
CompSysTech '03 Proceedings of the 4th international conference conference on Computer systems and technologies: e-Learning
Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation
Proceedings of the 1st conference on Computing frontiers
A methodology for low power scheduling with resources operating at multiple voltages
Integration, the VLSI Journal
Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Automatic translation of software binaries onto FPGAs
Proceedings of the 41st annual Design Automation Conference
A recursive paradigm to solve Boolean relations
Proceedings of the 41st annual Design Automation Conference
Fast hazard detection in combinational circuits
Proceedings of the 41st annual Design Automation Conference
RTL Power Optimization with Gate-Level Accuracy
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Gradual Relaxation Techniques with Applications to Behavioral Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A procedure for obtaining a behavioral description for the control logic of a non-linear pipeline
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Efficient computation of canonical form for Boolean matching in large libraries
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Compiler-directed code restructuring for reducing data TLB energy
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization
Journal of VLSI Signal Processing Systems
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exploiting Program Branch Probabilities in Hardware Compilation
IEEE Transactions on Computers
Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices
IEEE Transactions on Parallel and Distributed Systems
Input space adaptive design: a high-level methodology for optimizing energy and performance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A software/reconfigurable hardware SAT solver
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems
IEEE Transactions on Computers
A behavioral synthesis system for asynchronous circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bipartitioning and encoding in low-power pipelined circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction set extension with shadow registers for configurable processors
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
An ILP Formulation for Reliability-Oriented High-Level Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Reliability-Centric Hardware/Software Co-Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Customisable Hardware Compilation
The Journal of Supercomputing
Synthesis of application-specific highly efficient multi-mode cores for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Instruction scheduling using MAX-MIN ant system optimization
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Multi-GHz SiGe design methodologies for reconfigurable computing
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimum and heuristic synthesis of multiple word-length architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MP core: algorithm and design techniques for efficient channel estimation in wireless applications
Proceedings of the 42nd annual Design Automation Conference
A new canonical form for fast boolean matching in logic synthesis and verification
Proceedings of the 42nd annual Design Automation Conference
Effective bounding techniques for solving unate and binate covering problems
Proceedings of the 42nd annual Design Automation Conference
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips
Proceedings of the 42nd annual Design Automation Conference
Journal of Systems Architecture: the EUROMICRO Journal
Synthesis of Self-Resetting Stage Logic Pipelines
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Encyclopedia of Computer Science
Behavioral synthesis techniques for intellectual property protection
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An o(min(m, n)) parallel deadlock detection algorithm
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integration, the VLSI Journal
High-level synthesis for large bit-width multipliers on FPGAs: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An application of functional decomposition in ROM-based FSM implementation in FPGA devices
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable embedded systems: Synthesis, design and application
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Equivalence checking of arithmetic expressions using fast evaluation
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Optimizing Hardware Function Evaluation
IEEE Transactions on Computers
IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB)
DAG-aware circuit compression for formal verification
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Architectural-level synthesis of digital microfluidics-based biochips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Worst case execution time analysis for synthesized hardware
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Statistical Bellman-Ford algorithm with an application to retiming
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An overview of a compiler for mapping MATLAB programs onto FPGAs
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Scalable interprocedural register allocation for high level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal module and voltage assignment for low-power
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Bitwidth-aware scheduling and binding in high-level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Automatic extraction of function bodies from software binaries
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An interactive codesign environment for domain-specific coprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Loop scheduling with timing and switching-activity minimization for VLIW DSP
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Minimizing FPGA Reconfiguration Data at Logic Level
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Scheduling under resource constraints using dis-equations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Optimizing system models for simulation efficiency
Formal methods and models for system design
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards the automatic exploration of arithmetic-circuit architectures
Proceedings of the 43rd annual Design Automation Conference
Synthesis of high-performance packet processing pipelines
Proceedings of the 43rd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units
The Journal of Supercomputing
Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs
Proceedings of the 2006 international symposium on Low power electronics and design
A method for the minimum coloring problem using genetic algorithms
MS'06 Proceedings of the 17th IASTED international conference on Modelling and simulation
Crosstalk minimization in logic synthesis for PLAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multiple wire reconnections based on implication flow graph
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms
Microprocessors & Microsystems
Theory of wire addition and removal in combinational Boolean networks
Microelectronic Engineering
Managing the power resources of sensor networks with performance considerations
Computer Communications
A high-level register optimization technique for minimizing leakage and dynamic power
Proceedings of the 17th ACM Great Lakes symposium on VLSI
The Journal of Supercomputing
Cost-aware synthesis of asynchronous circuits based on partial acknowledgement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
The Journal of Supercomputing
A unified evaluation framework for coarse grained reconfigurable array architectures
Proceedings of the 4th international conference on Computing frontiers
Computer-Aided Design and Test for Digital Microfluidics
IEEE Design & Test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Speedups in embedded systems with a high-performance coprocessor datapath
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data-flow transformations using Taylor expansion diagrams
Proceedings of the conference on Design, automation and test in Europe
Reversible circuit technology mapping from non-reversible specifications
Proceedings of the conference on Design, automation and test in Europe
Interactive presentation: Improving the fault tolerance of nanometric PLA designs
Proceedings of the conference on Design, automation and test in Europe
Using Transport Triggered Architectures for Embedded Processor Design
Integrated Computer-Aided Engineering
Hardware/Software Co-Design Methodology for Design of Embedded Systems
Integrated Computer-Aided Engineering
Optimization of polynomial datapaths using finite ring algebra
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Progressive decomposition: a heuristic to structure arithmetic circuits
Proceedings of the 44th annual Design Automation Conference
High-contrast algorithm behavior: observation, hypothesis, and experimental design
Proceedings of the 2007 workshop on Experimental computer science
High-contrast algorithm behavior: observation, conjecture, and experimental design
ecs'07 Experimental computer science on Experimental computer science
Performance testing of combinatorial solvers with isomorph class instances
ecs'07 Experimental computer science on Experimental computer science
FPGA implementation of an MUD based on cascade filters for a WCDMA system
EURASIP Journal on Applied Signal Processing
Thread warping: a framework for dynamic synthesis of thread accelerators
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
High-level synthesis of digital microfluidic biochips
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Using functional independence conditions to optimize the performance of latency-insensitive systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing variation-aware high-level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Engineering change using spare cells with constant insertion
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A design flow dedicated to multi-mode architectures for DSP applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP
Journal of Parallel and Distributed Computing
Near-optimal instruction selection on dags
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Algorithms and analysis of scheduling for loops with minimum switching
International Journal of Computational Science and Engineering
An incremental temporal partitioning method for real-time reconfigurable systems
EHAC'06 Proceedings of the 5th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Energy saving for memory with loop scheduling and prefetching
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A multi-mode video-stream processor with cyclically reconfigurable architecture
Proceedings of the 5th conference on Computing frontiers
Optimized mapping for enchancing the operation parallelism in coarse-grained reconfigurable arrays
SMO'06 Proceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization
An ILP based management protocol for wireless networks
ICCOM'05 Proceedings of the 9th WSEAS International Conference on Communications
Time-constrained loop scheduling with minimal resources
Journal of Embedded Computing - Embeded Processors and Systems: Architectural Issues and Solutions for Emerging Applications
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Journal of Signal Processing Systems
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
An overview of a compiler for mapping software binaries to hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synthesis of FSMs on the basis of reusable hardware templates
ISTASC'06 Proceedings of the 6th WSEAS International Conference on Systems Theory & Scientific Computation
Column-matching based mixed-mode test pattern generator design technique for BIST
Microprocessors & Microsystems
Power-gating-aware high-level synthesis
Proceedings of the 13th international symposium on Low power electronics and design
An architecture framework for an adaptive extensible processor
The Journal of Supercomputing
Temperature-aware scheduling and assignment for hard real-time applications on MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Contract-Based Design for Computation and Verification of a Closed-Loop Hybrid System
HSCC '08 Proceedings of the 11th international workshop on Hybrid Systems: Computation and Control
Interconnect customization for a hardware fabric
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A novel Boolean algebraic framework for association and pattern mining
WSEAS Transactions on Computers
Note: Minimization of circuit registers: Retiming revisited
Discrete Applied Mathematics
Integrated floorplanning, module-selection, and architecture generation for reconfigurable devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel approach for fast covering the Boolean sets
ISTASC'08 Proceedings of the 8th conference on Systems theory and scientific computation
On optimisation of the rough set-based decision rule extraction
ACS'08 Proceedings of the 8th conference on Applied computer scince
Smart Enumeration: A Systematic Approach to Exhaustive Search
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Timing driven power gating in high-level synthesis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Area optimisation for field-programmable gate arrays in SystemC hardware compilation
International Journal of Reconfigurable Computing - Selected Papers from SPL 2008: Programmable Logic and Applications
A Boolean algebraic framework for association and pattern mining
ICCOMP'08 Proceedings of the 12th WSEAS international conference on Computers
Resource aware mapping on coarse grained reconfigurable arrays
Microprocessors & Microsystems
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Max-Flow Scheduling in High-Level Synthesis
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A New Datapath Merging Method for Reconfigurable System
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Evolutionary Optimization of Number of Gates in PLA Circuits Implemented in VLSI Circuits
EvoWorkshops '09 Proceedings of the EvoWorkshops 2009 on Applications of Evolutionary Computing: EvoCOMNET, EvoENVIRONMENT, EvoFIN, EvoGAMES, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, EvoNUM, EvoSTOC, EvoTRANSLOG
Loop scheduling and bank type assignment for heterogeneous multi-bank memory
Journal of Parallel and Distributed Computing
Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays
The Journal of Supercomputing
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
An interactive design environment for C-based high-level synthesis of RTL processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust power gating structure and power mode transition strategy for MTCMOS design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sleepy stack leakage reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture
Journal of Signal Processing Systems
A fault tolerant threshold logic gate design
ICC'09 Proceedings of the 13th WSEAS international conference on Circuits
Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Resurrecting infeasible clock-gating functions
Proceedings of the 46th Annual Design Automation Conference
Timing-driven optimization using lookahead logic circuits
Proceedings of the 46th Annual Design Automation Conference
Register allocation for high-level synthesis using dual supply voltages
Proceedings of the 46th Annual Design Automation Conference
Optimization of a logic circuit implementing a Moore automaton in CPLD basis
Cybernetics and Systems Analysis
Efficient RNAi-based gene family knockdown via set cover optimization
Artificial Intelligence in Medicine
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis and optimization of pipelined packet processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Spare cells with constant insertion for engineering change
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An outlook on design technologies for future integrated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An RNS implementation of an Fpelliptic curve point multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of data-flow computations using canonical TED representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scheduling with soft constraints
Proceedings of the 2009 International Conference on Computer-Aided Design
Iterative layering: optimizing arithmetic circuits by structuring the information flow
Proceedings of the 2009 International Conference on Computer-Aided Design
Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network
ICIC '07 Proceedings of the 3rd International Conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications. With Aspects of Artificial Intelligence
Logic synthesis based on decomposition for CPLDs
Microprocessors & Microsystems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integration, the VLSI Journal
Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM
International Journal of Applied Mathematics and Computer Science
Synthesis of finite state machines for CPLDs
International Journal of Applied Mathematics and Computer Science - Special Section: Robot Control Theory Cezary Zielinski
Bit-level optimization for high-level synthesis and FPGA-based acceleration
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Concurrent BIST synthesis and test scheduling using genetic algorithms
International Journal of Computers and Applications
Scheduling framework for real-time dependable NoC-based systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
Reference traces by simulation for tracking control-logic
ETFA'09 Proceedings of the 14th IEEE international conference on Emerging technologies & factory automation
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Rapid prototyping methodology and environments for fuzzy applications
ICCS'03 Proceedings of the 2003 international conference on Computational science
RECOMB'07 Proceedings of the 11th annual international conference on Research in computational molecular biology
Complexity reduction for the design of interacting controllers
HSCC'07 Proceedings of the 10th international conference on Hybrid systems: computation and control
A SVD-based fragile watermarking scheme for image authentication
IWDW'02 Proceedings of the 1st international conference on Digital watermarking
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Scalable identification of threshold logic functions
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Timing variation-aware high-level synthesis considering accurate yield computation
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Translation validation of high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design automation and test solutions for digital microfluidic biochips
IEEE Transactions on Circuits and Systems Part I: Regular Papers
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LUT-based FPGA technology mapping for reliability
Proceedings of the 47th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Covering strategies for library free technology mapping
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the Conference on Design, Automation and Test in Europe
Coordinated resource optimization in behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
DynAHeal: dynamic energy efficient task assignment for wireless healthcare systems
Proceedings of the Conference on Design, Automation and Test in Europe
Using speculative functional units in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
HLS-l: high-level synthesis of high performance latch-based circuits
Proceedings of the Conference on Design, Automation and Test in Europe
SEU-aware resource binding for modular redundancy based designs on FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
GCS: high-performance gate-level simulation with GP-GPUs
Proceedings of the Conference on Design, Automation and Test in Europe
An MILP-based performance analysis technique for non-preemptive multitasking MPSoC
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Parallel evolutionary approach of compaction problem using mapreduce
PPSN'10 Proceedings of the 11th international conference on Parallel problem solving from nature: Part II
Code scheduling for optimizing parallelism and data locality
EuroPar'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A probabilistic Boolean logic for energy efficient circuit and system design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A novel SAT-based approach to the task graph cost-optimal scheduling problem
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level synthesis for designing multimode architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Smalltalk debug lives in the matrix
IWST '10 International Workshop on Smalltalk Technologies
Code transformations for embedded reconfigurable computing architectures
GTTSE'09 Proceedings of the 3rd international summer school conference on Generative and transformational techniques in software engineering III
Variable assignment and instruction scheduling for processor with multi-module memory
Microprocessors & Microsystems
Optimization of circuits of compositional microprogram control units implemented on FPGA
Cybernetics and Systems Analysis
Pipelining with common operands for power-efficient linear systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Expression equivalence checking using interval analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Probabilistic delay budget assignment for synthesis of soft real-time applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scenario-oriented design for single-chip heterogeneous multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Overview of a compiler for synthesizing MATLAB programs onto FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level synthesis of in-circuit assertions for verification, debugging, and timing analysis
International Journal of Reconfigurable Computing - Special issue on selected papers from the 17th reconfigurable architectures workshop (RAW2010)
SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Scheduling and resource binding algorithm considering timing variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance and area efficient flexible DSP datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient retiming of large circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Behavioral synthesis of asynchronous circuits using syntax directed translation as backend
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing variation-aware scheduling and resource binding in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level modeling and synthesis of flow-based microfluidic biochips
CASES '11 Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems
A design methodology to implement memory accesses in high-level synthesis
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
High level synthesis of asynchronous circuits from data flow graphs
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Decomposition-based logic synthesis for PAL-based CPLDs
International Journal of Applied Mathematics and Computer Science
Reduction in the number of LUT elements for control units with code sharing
International Journal of Applied Mathematics and Computer Science
Design of microprogrammed controllers to be implemented in FPGAs
International Journal of Applied Mathematics and Computer Science - SPECIAL SECTION: Efficient Resource Management for Grid-Enabled Applications
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Area and speed oriented synthesis of FSMs for PAL-based CPLDs
Microprocessors & Microsystems
Jaguar: a compiler infrastructure for java reconfigurable computing
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Efficient evolutionary approaches for the data ordering problem with inversion
EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing
A novel task scheduling for heterogeneous systems
ICESS'04 Proceedings of the First international conference on Embedded Software and Systems
The role of EDA in digital print automation and infrastructure optimization
Proceedings of the International Conference on Computer-Aided Design
An energy and power-aware approach to high-level synthesis of asynchronous systems
Proceedings of the International Conference on Computer-Aided Design
Clustering-based simultaneous task and voltage scheduling for NoC systems
Proceedings of the International Conference on Computer-Aided Design
Bi-decomposition of large Boolean functions using blocking edge graphs
Proceedings of the International Conference on Computer-Aided Design
Design methodology for context-aware wearable sensor systems
PERVASIVE'05 Proceedings of the Third international conference on Pervasive Computing
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
An integrated partitioning and scheduling based branch decoupling
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Policy-driven memory protection for reconfigurable hardware
ESORICS'06 Proceedings of the 11th European conference on Research in Computer Security
Proceedings of the great lakes symposium on VLSI
EDA for secure and dependable cybercars: challenges and opportunities
Proceedings of the 49th Annual Design Automation Conference
SALSA: systematic logic synthesis of approximate circuits
Proceedings of the 49th Annual Design Automation Conference
What to do about the end of Moore's law, probably!
Proceedings of the 49th Annual Design Automation Conference
Unrolling and retiming of stream applications onto embedded multicore processors
Proceedings of the 49th Annual Design Automation Conference
Elastic computing: A portable optimization framework for hybrid computers
Parallel Computing
CCP: common case promotion for improved timing error resilience with energy efficiency
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
A coarse-grained reconfigurable architecture with compilation for high performance
International Journal of Reconfigurable Computing - Special issue on High-Performance Reconfigurable Computing
Architectural synthesis of flow-based microfluidic large-scale integration biochips
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A Heuristic for reducing dynamic power dissipation in clocked sequential designs
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
On the Evolution of Hardware Circuits via Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Scalable sampling methodology for logic simulation: reduced-ordered Monte Carlo
Proceedings of the International Conference on Computer-Aided Design
Distributed memory interface synthesis for network-on-chips with 3D-stacked DRAMs
Proceedings of the International Conference on Computer-Aided Design
Low-power anti-aging zero skew clock gating
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Eliminating the Timing Penalty of Scan
Journal of Electronic Testing: Theory and Applications
Ten Years of Building Broken Chips: The Physics and Engineering of Inexact Computing
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
FPGA latency optimization using system-level transformations and DFG restructuring
Proceedings of the Conference on Design, Automation and Test in Europe
Scheduling independent liveness analysis for register binding in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition
Proceedings of the 50th Annual Design Automation Conference
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling static-order schedules in synchronous dataflow graphs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting area/delay tradeoffs in high-level synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
ITRS 2011 analog EDA challenges and approaches
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Multi-token resource sharing for pipelined asynchronous systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Symmetry breaking for multi-criteria mapping and scheduling on multicores
FORMATS'13 Proceedings of the 11th international conference on Formal Modeling and Analysis of Timed Systems
Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The benefits of using variable-length pipelined operations in high-level synthesis
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Encoding multi-valued functions for symmetry
Proceedings of the International Conference on Computer-Aided Design
Approximate logic synthesis under general error magnitude and frequency constraints
Proceedings of the International Conference on Computer-Aided Design
Reducing the Use of Resources in the FPGA Circuit of a Moore FSM
Cybernetics and Systems Analysis
Web Intelligence and Agent Systems
Dynamic policy adaptation for inference control of queries to a propositional information system
Journal of Computer Security - DBSec 2011
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From the Publisher:Synthesis and Optimization of Digital Circuits offers a modern, up-to-date look at computer-aided design (CAD) of very large-scale integration (VLSI) circuits. In particular, this book covers techniques for synthesis and optimization of digital circuits at the architectural and logic levels, i.e., the generation of performance-and/or area-optimal circuits representations from models in hardware description languages. The book provides a thorough explanation of synthesis and optimization algorithms accompanied by a sound mathematical formulation and a unified notation. The text covers the following topics: modern hardware description languages (e.g., VHDL, Verilog); architectural-level synthesis of data flow and control units, including algorithms for scheduling and resource binding; combinational logic optimization algorithms for two-level and multiple-level circuits; sequential logic optimization methods; and library binding techniques, including those applicable to FPGAs.