Experience with ADAM synthesis system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A recursive technique for computing lower-bound performance of schedules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
Estimation of lower bounds in scheduling algorithms for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Retargetable Compilers for Embedded Core Processors: Methods and Experience in Industrial Applications
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Digital Signal Processing: A Practical Approach
Digital Signal Processing: A Practical Approach
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Traditional lower bound estimates on latency for dataflow graphs assume no data transfer delays. While such approaches can generate tight lower bounds for datapaths with a centralized register file, the results may be uninformative for datapaths with distributed register file structures that are characteristic of VLIW ASIPs. In this paper we propose a latency bound that accounts for such data transfer delays. The novelty of our approach lies in construction the "window dependency graph" and bounds associated with the problem which capture delay penalties due to operation serialization and/or data moves among distributed register files. Through a set of benchmark examples, we show that the bound is competitive with state-of-the-art approaches. Moreover, our experiments show that the approach can aid an iterative improvement algorithm in determining good functional unit assignment ?-- a key step in code generation for VLIW ASIPs.