Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator

  • Authors:

  • Silvina Hanono;Srinivas Devadas

  • Affiliations:

  • Department of EECS, MIT;Department of EECS, MIT

  • Venue:
  • DAC '98 Proceedings of the 35th annual Design Automation Conference
  • Year:
  • 1998

Quantified Score

Hi-index 0.00

Visualization

Abstract

The AVIV retargetable code generator produces optimized machine code for target processors with different instruction set architectures AVIV optimizes for minimum code size.Retargetable code generation requires the development of heuristic algorithms for instruction selection, resource allocation, and scheduling. AVIV addresses these code generation subproblems concurrently, whereas most current code generation systems address them sequentially. It accomplishes this by converting the input application to a graphical (Split-Node DAG) representation that specifies all possible ways of implementing the application on the target processor. The information embedded in this representation in then used to set up a heuristic branch-and-bound step that performs functional unit assignment, operation grouping, register bank allocation, and scheduling concurrently. While detailed register allocation is carried out as a second step, estimates of register requirements are generated during the first step to ensure high quality of the final assembly code.We show that near-optimal code can be generated for basic blocks for different architectures within reasonable amounts of CPU time. Our framework thus allows us to accurately evaluate the performance of different architectures on application code.