Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Lazy data routing and greedy scheduling for application-specific signal processors
MICRO 21 Proceedings of the 21st annual workshop on Microprogramming and microarchitecture
Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
BEG: a generator for efficient back ends
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Optimizing stack frame accesses for processors with restricted addressing modes
Software—Practice & Experience
Engineering a simple, efficient code-generator generator
ACM Letters on Programming Languages and Systems (LOPLAS)
Storage assignment to decrease code size
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Conflict modelling and instruction scheduling in code generation for in-house DSP cores
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Optimal code generation for embedded memory non-homogeneous register architectures
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Memory bank and register allocation in software synthesis for ASIPs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Exploiting dual data-memory banks in digital signal processors
Proceedings of the seventh international conference on Architectural support for programming languages and operating systems
Using register-transfer paths in code generation for heterogeneous memory-register architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algorithms for address assignment in DSP code generation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Modern complier implementation in C: basic techniques
Modern complier implementation in C: basic techniques
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An integrated approach to retargetable code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Tree-based mapping of algorithms to predefined structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Analysis and evaluation of address arithmetic capabilities in custom DSP architectures
DAC '97 Proceedings of the 34th annual Design Automation Conference
Low energy memory and register allocation using network flow
DAC '97 Proceedings of the 34th annual Design Automation Conference
Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator
DAC '98 Proceedings of the 35th annual Design Automation Conference
Advanced compiler design and implementation
Advanced compiler design and implementation
A uniform optimization technique for offset assignment problems
Proceedings of the 11th international symposium on System synthesis
Storage assignment optimizations to generate compact and efficient code on embedded DSPs
Proceedings of the ACM SIGPLAN 1999 conference on Programming language design and implementation
Memory aware compilation through accurate timing extraction
Proceedings of the 37th Annual Design Automation Conference
Function inlining under code size constraints for embedded processors
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Code selection for media processors with SIMD instructions
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Analysis of high-level address code transformations for programmable processors
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Register allocation for common subexpressions in DSP data paths
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Retargetable Code Generation for Digital Signal Processors
Retargetable Code Generation for Digital Signal Processors
Retargetable Compilers for Embedded Core Processors: Methods and Experience in Industrial Applications
Loop Transformations for Restructuring Compilers: The Foundations
Loop Transformations for Restructuring Compilers: The Foundations
Code Generation for Embedded Processors
Code Generation for Embedded Processors
A Development Environment for Horizontal Microcode
IEEE Transactions on Software Engineering
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Constructing Memory Layouts for Address Generation Units Supporting Offset 2 Access
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 1 - Volume 1
Efficient Scheduling of DSP Code on Processors with Distributed Register Files
Proceedings of the 12th international symposium on System synthesis
Towards direct execution of esterel programs on reactive processors
Proceedings of the 4th ACM international conference on Embedded software
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
Usability evaluation of Korean e-government portal
UAHCI'07 Proceedings of the 4th international conference on Universal access in human-computer interaction: applications and services
Storage Optimization through Offset Assignment with Variable Coalescing
ACM Transactions on Embedded Computing Systems (TECS)
An ILP solution to address code generation for embedded applications on digital signal processors
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Minimizing address arithmetic instructions in embedded applications on DSPs
Computers and Electrical Engineering
Integrated modulo scheduling and cluster assignment for TI TMS320C64x+ architecture
Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems
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The increasing use of programmable processors as IP blocks in embedded system design creates a need for C/C++ compilers capable of generating efficient machine code. Many of today's compilers for embedded processors suffer from insufficient code quality in terms of code size and performance. This violates the tight chip area and real-time constraints often imposed on embedded systems. The reason is that embedded processors typically show architectural features which are not well handled by classical compiler technology. This paper provides a survey of methods and techniques dedicated to efficient code generation for embedded processors. Emphasis is put on DSP and multimedia processors, for which better compiler technology is definitely required. In addition, some frontend aspects and recent trends in research and industry are briefly covered. The goal of these recent efforts in embedded code generation is to facilitate the step from assembly to high-level language programming of embedded systems, so as to provide higher productivity, dependability, and portability of embedded software.