Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Optimal register assignment to loops for embedded code generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An efficient model for DSP code generation: performance, code size, estimated energy
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Education for the deep submicron age: business as usual?
DAC '97 Proceedings of the 34th annual Design Automation Conference
DSP address optimization using a minimum cost circulation technique
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Scheduling and binding bounds for RT-level symbolic execution
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Transformational partitioning for co-design of multiprocessor systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Memory data organization for improved cache performance in embedded processor applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code placement techniques for cache miss rate reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The construction of a retargetable simulator for an architecture template
Proceedings of the 6th international workshop on Hardware/software codesign
Code generation for fixed-point DSPs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HDL-based modeling of embedded processor behavior for retargetable compilation
Proceedings of the 11th international symposium on System synthesis
Constraint driven code selection for fixed-point DSPs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Heuristic tradeoffs between latency and energy consumption in register assignment
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Lower bound on latency for VLIW ASIP datapaths
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Shared memory implementations of synchronous dataflow specifications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Graph-based code selection techniques for embedded processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new approach to assembly software retargeting for microcontrollers
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Register allocation for common subexpressions in DSP data paths
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ILP-based Instruction Scheduling for IA-64
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
A Dynamic Programming Approach to Optimal Integrated Code Generation
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Code generation for embedded processors
ISSS '00 Proceedings of the 13th international symposium on System synthesis
The very portable optimizer for digital signal processors
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
A software development tool chain for a reconfigurable processor
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Generic control flow reconstruction from assembly code
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
VISTA: a system for interactive code improvement
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Quick piping: a fast, high-level model for describing processor pipelines
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Address assignment combined with scheduling in DSP code generation
Proceedings of the 39th annual Design Automation Conference
Complex library mapping for embedded software using symbolic algebra
Proceedings of the 39th annual Design Automation Conference
Design of embedded systems: formal models, validation, and synthesis
Readings in hardware/software co-design
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Lower bound on latency for VLIW ASIP datapaths
Readings in hardware/software co-design
Constraint analysis for DSP code generation
Readings in hardware/software co-design
Experience with a retargetable compiler for a commercial network processor
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Synthesis of Embedded Software from Synchronous Dataflow Specifications
Journal of VLSI Signal Processing Systems
Exploring performance tradeoffs for clustered VLIW ASIPs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
System-on-a-Chip Cosimulation and Compilation
IEEE Design & Test
Design Challenges for New Application-Specific Processors
IEEE Design & Test
Embedded Tools for a Configurable and Customizable DSP Architecture
IEEE Design & Test
Improving Offset Assignment on Embedded Processors Using Transformations
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Improving Offset Assignment for Embedded Processors
LCPC '00 Proceedings of the 13th International Workshop on Languages and Compilers for Parallel Computing-Revised Papers
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Design Tools for Application Specific Embedded Processors
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
PROPAN: A Retargetable System for Postpass Optimisations and Analyses
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
TAO: regular expression based high-level testability analysis and optimization
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A network flow approach to memory bandwidth utilization in embedded DSP core processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Operation Serializability for Embedded Systems
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Industrial approach in design methodologies for mobile communications systems
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Instruction-Set Modeling for ASIP Code Generation
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Shake And Bake: A Method of Mapping Code to Irregular DSPs
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Symbolic Binding for Clustered VLIW ASIPs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Size-Constrained Code Placement for Cache Miss Rate Reduction
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Memory Organization for Improved Data Cache Performance in Embedded Processors
ISSS '96 Proceedings of the 9th international symposium on System synthesis
A Buffer Merging Technique for Reducing Memory Requirements of Synchronous Dataflow Specifications
Proceedings of the 12th international symposium on System synthesis
Using Graph Models in Retargetable Optimizing Compilers for Microprocessors with VLIW Architectures
Cybernetics and Systems Analysis
SystemC
Increasing the number of effective registers in a low-power processor using a windowed register file
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
TDL: a hardware description language for retargetable postpass optimizations and analyses
Proceedings of the 2nd international conference on Generative programming and component engineering
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization
Journal of VLSI Signal Processing Systems
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Proceedings of the 32nd annual international symposium on Computer Architecture
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor
IEEE Transactions on Computers
Retargetable code generation for application-specific processors
Future Generation Computer Systems - Special issue: Parallel computing technologies
Generic software pipelining at the assembly level
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Efficient simulation of critical synchronous dataflow graphs
Proceedings of the 43rd annual Design Automation Conference
Efficient Techniques for Clustering and Scheduling onto Embedded Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
VISTA: VPO interactive system for tuning applications
ACM Transactions on Embedded Computing Systems (TECS)
Efficient simulation of critical synchronous dataflow graphs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Modulo scheduling for highly customized datapaths to increase hardware reusability
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Processor Description Languages
Processor Description Languages
Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers
Transactions on High-Performance Embedded Architectures and Compilers II
Retargetable code generation for application-specific processors
Future Generation Computer Systems - Special issue: Parallel computing technologies
MTPP'10 Proceedings of the Second Russia-Taiwan conference on Methods and tools of parallel programming multicomputers
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Integration of Dataflow-Based Heterogeneous Multiprocessor Scheduling Techniques in GNU Radio
Journal of Signal Processing Systems
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
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From the Publisher:Modern electronics is driven by the explosive growth of digital communications and multi-media technology. A basic challenge is to design first-time-right complex digital systems, that meet stringent constraints on performance and power dissipation. In order to combine this growing system complexity with an increasingly short time-to-market, new system design technologies are emerging based on the paradigm of embedded programmable processors. This concept introduces modularity, flexibility and re-use in the electronic system design process. However, its success will critically depend on the availability of efficient and reliable CAD tools to design, programme and verify the functionality of embedded processors. Recently, new research efforts emerged on the edge between software compilation and hardware synthesis, to develop high-quality code generation tools for embedded processors. Code Generation for Embedded Processors provides a survey of these new developments. Although not limited to these targets, the main emphasis is on code generation for modern DSP processors. Important themes covered by the book include: the scope of general purpose versus application-specific processors, machine code quality for embedded applications, retargetability of the code generation process, machine description formalisms, and code generation methodologies. Code Generation for Embedded Processors is the essential introduction to this fast developing field of research for students, researchers, and practitioners alike.