Code selection through object code optimization
ACM Transactions on Programming Languages and Systems (TOPLAS) - Lecture notes in computer science Vol. 174
Affix grammar driven code generation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Bulldog: a compiler for VLSI architectures
Bulldog: a compiler for VLSI architectures
Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Optimal code generation for expression trees: an application BURS theory
POPL '88 Proceedings of the 15th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
BEG: a generator for efficient back ends
PLDI '89 Proceedings of the ACM SIGPLAN 1989 Conference on Programming language design and implementation
Code generation using tree matching and dynamic programming
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The priority-based coloring approach to register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Selected papers of the second workshop on Languages and compilers for parallel computing
Register allocation via hierarchical graph coloring
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Code duplication: an assist for global instruction scheduling
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Architecture and programming of a VLIW style programmable video signal processor
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
BURG: fast optimal instruction selection and tree parsing
ACM SIGPLAN Notices
Optimizing stack frame accesses for processors with restricted addressing modes
Software—Practice & Experience
Simple and efficient BURS table generation
PLDI '92 Proceedings of the ACM SIGPLAN 1992 conference on Programming language design and implementation
Enhanced region scheduling on a program dependence graph
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Engineering a simple, efficient code-generator generator
ACM Letters on Programming Languages and Systems (LOPLAS)
Register allocation with instruction scheduling
PLDI '93 Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation
Register allocation via graph coloring
Register allocation via graph coloring
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Dependence-conscious global register allocation
Proceedings of the international conference on Programming languages and system architectures
Storage assignment to decrease code size
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Optimal code generation for embedded memory non-homogeneous register architectures
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Time-constrained code compaction for DSPs
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Industrial experience using rule-driven retargetable code generation for multimedia applications
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Memory bank and register allocation in software synthesis for ASIPs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Address calculation for retargetable compilation and exploration of instruction-set architectures
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Algorithms for address assignment in DSP code generation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Instruction selection for embedded DSPs with complex instructions
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Data routing: a paradigm for efficient data-path synthesis and code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An integrated approach to retargetable code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
A software pipelining based VLIW architecture and optimizing compiler
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
GURPR—a method for global software pipelining
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
Tree-based mapping of algorithms to predefined structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The Generation of Optimal Code for Arithmetic Expressions
Journal of the ACM (JACM)
Optimal Code Generation for Expression Trees
Journal of the ACM (JACM)
Code Generation for a One-Register Machine
Journal of the ACM (JACM)
Code Generation for Expressions with Common Subexpressions
Journal of the ACM (JACM)
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
The Design and Application of a Retargetable Peephole Optimizer
ACM Transactions on Programming Languages and Systems (TOPLAS)
A new method for compiler code generation
POPL '78 Proceedings of the 5th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Code Generation for Embedded Processors
Code Generation for Embedded Processors
Compiler Design
A BDD-based frontend for retargetable compilers
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Describing instruction set processors using nML
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Graph Based Processor Model for Retargetable Code Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Phase coupling and constant generation in an optimizing microcode compiler
MICRO 15 Proceedings of the 15th annual workshop on Microprogramming
ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
An experiment in table driven code generation
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Percolation Scheduling: A Parallel Compilation Technique
Percolation Scheduling: A Parallel Compilation Technique
Code generation and optimization for embedded digital signal processors
Code generation and optimization for embedded digital signal processors
Computer structures: Readings and examples (McGraw-Hill computer science series)
Computer structures: Readings and examples (McGraw-Hill computer science series)
Compiling concurrent programs for embedded sequential execution
Integration, the VLSI Journal
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The increasing use of embedded software, often implemented on a core processor in a single-chip system, is a clear trend in the telecommunications, multimedia, and consumer electronics industries. A companion paper in this issue (1) presents a survey of application and architecture trends for embedded systems in these growth markets. However, the lack of suitable design technology remains a significant obstacle in the development of such systems. One of the key requirements is more efficient software compilation technology. Especially in the case of fixed-point digital signal processor (DSP) cores, it is often cited that commercially available compilers are unable to take full advantage of the architectural features of the processor. Moreover, due to the shorter lifetimes and the architectural specialization of many processor cores, processor designers are often compelled to neglect the issue of compiler support.