SAMP: a general purpose processor based on a self-timed VLIW structure
ACM SIGARCH Computer Architecture News
Graph based retargetable microcode compilation in the MIMOLA design system
MICRO 20 Proceedings of the 20th annual workshop on Microprogramming
A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic generation of self-test programs—a new feature of the MIMOLA design system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Retargetable Compiler Code Generation
ACM Computing Surveys (CSUR)
The mimola design system: Tools for the design of digital processors
DAC '84 Proceedings of the 21st Design Automation Conference
A retargetable compiler for a high-level microprogramming language
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Global methods in the flow graph approach to retargetable microcode generation
MICRO 17 Proceedings of the 17th annual workshop on Microprogramming
Local code generation and compaction in optimizing microcode compilers
Local code generation and compaction in optimizing microcode compilers
Optimization and resynthesis of complex data-paths
DAC '93 Proceedings of the 30th international Design Automation Conference
Instruction set extraction from programmable structures
EURO-DAC '94 Proceedings of the conference on European design automation
Generating compilers for generated datapaths
EURO-DAC '94 Proceedings of the conference on European design automation
Retargetable self-test program generation using constraint logic programming
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Instruction selection for embedded DSPs with complex instructions
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Instruction set definition and instruction selection for ASIPs
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
An integrated approach to retargetable code generation
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Retargetable assembly code generation by bootstrapping
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Tree-based mapping of algorithms to predefined structures
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Embedded software in real-time signal processing systems: design technologies
Readings in hardware/software co-design
Simulation-Based Verification for High-Level Synthesis
IEEE Design & Test
A BDD-based frontend for retargetable compilers
EDTC '95 Proceedings of the 1995 European conference on Design and Test
A Graph Based Processor Model for Retargetable Code Generation
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Retargetable Generation of Code Selectors from HDL Processor Models
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Processor Description Languages
Processor Description Languages
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This paper proposes a new method for hardware verification. The basic idea is the application of a retargetable compiler as verification tool. A retargetable compiler is able to compile programs into the machine code of a specified hardware (target). If the program is the complete behavioural specification of the target, the compiler can be used to verify that a properly programmed structure implements the behaviour. Methods, algorithms and applications of an existing retargetable compiler are described.