Process-graph analyser: a front-end tool for VHDL behavioural synthesis
Software—Practice & Experience
Verification of hardware descriptions by retargetable code generation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
The system architect's workbench
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Bridge: a versatile behavioral synthesis system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A D&T Roundtable-Formal Verification: Is It Practical for Real-World Design?
IEEE Design & Test
The second generation motis mixed-mode simulator
DAC '84 Proceedings of the 21st Design Automation Conference
High-level synthesis of digital circuits using global scheduling and binding algorithms
High-level synthesis of digital circuits using global scheduling and binding algorithms
Simulation based verification of register-transfer level behavioral synthesis tools
EURO-DAC '90 Proceedings of the conference on European design automation
Experiences in functional validation of a high level synthesis system
DAC '93 Proceedings of the 30th international Design Automation Conference
Verification by simulation comparison using interface synthesi
Proceedings of the conference on Design, automation and test in Europe
Observable Time Windows: Verifying High-Level Synthesis Results
IEEE Design & Test
Observable Time Windows: Verifying the Results of High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Simulation bounds for equivalence verification of polynomial datapaths using finite ring algebra
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The verification problem is described, and a way to verify a high-level synthesis system automatically is presented. The system, called Satya, maps an algorithmic description to a logic circuit description and compares descriptions to detect semantic errors and identify the cause of those errors. Satya has been used to verify the Bridge synthesis system, which accepts a subset of C as input, but the simulation-based approach underlying Satya is suitable for verifying synthesis systems that use other high-level languages, such as VHDL. The verification results are discussed, and some of the problems that arise in debugging and regression testing are considered.