Logic design of digital systems
Logic design of digital systems
The Silc silicon compiler: language and features
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A high level synthesis tool for MOS chip design
DAC '84 Proceedings of the 21st Design Automation Conference
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Representing conditional branches for high-level synthesis applications
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A global, dynamic register allocation and binding for a data path synthesis system
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level transformations for minimizing syntactic variances
DAC '93 Proceedings of the 30th international Design Automation Conference
High-level synthesis in an industrial environment
IBM Journal of Research and Development - Special issue: IBM CMOS technology
An algorithm to determine mutually exclusive operations in behavioral descriptions
Proceedings of the conference on Design, automation and test in Europe
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A global approach to improve conditional hardware reuse in high-level synthesis
Journal of Systems Architecture: the EUROMICRO Journal
Simulation-Based Verification for High-Level Synthesis
IEEE Design & Test
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Simulation based verification of register-transfer level behavioral synthesis tools
EURO-DAC '90 Proceedings of the conference on European design automation
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Design of a low power MPEG-1 motion vector reconstructor
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
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Bridge is a behavioral synthesis system being developed at AT&T Bell Laboratories. Two slicing techniques are implemented in this system to drive structural allocation; one is local slicing and the other is global slicing. Global slicing supports the synthesis of concurrent processes with a centralized control. A variable in a behavioral description can be either a storage element or a signal. The impacts of treating a variable as a signal on data flow scheduling, control flow scheduling, and lifetime analysis are discussed. Intelligent bindings of the variables in a behavioral description to registers and signals not only reduce the implementation cost but also improve the circuit performance. Using global slicing and signal variables, a mircoarchitecture model can sometimes be reduced to the view of a finite state machine or a combinational circuit. Experimental data for the behavioral descriptions of the Intel 8251 are presented.