Design of a low power MPEG-1 motion vector reconstructor

Authors:
M. A. Ochoa-Montiel;B. M. Al-Hashimi;P. Kollig
Affiliations:
University of Southampton, Southampton, UK;University of Southampton, Southampton, UK;Millbrook Technology Campus, Southampton, UK
Venue:
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Year:
2009

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Abstract

This paper describes the design of a low power MPEG-1 motion vector reconstructor using behavioural synthesis methodology. Various techniques, such as appropriate voltage scaling after clock and operations throughput selection, and reduction of multiplexer-based interconnection complexity are used to reduce power consumption. The design has been implemented based on a library components previously synthesised using Synplify ASIC with ST 0.12μm technology library. Functional validation of the design has been performed through timing simulation with ModelSim, whereas power analysis is based on the reports obtained with PrimePower from Synopsys. The proposed design dissipates 42% less power than a power unaware design operated at the maximum supply voltage of the library components, i.e. 1.32V.