Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Behavior-preserving transformations for high-level synthesis
Proceedings of the Mathematical Sciences Institute workshop on Hardware specification, verification and synthesis: mathematical aspects
Relational algebra as formalism for hardware design
EUROMICRO 93 Nineteenth EUROMICRO symposium on microprocessing and microprogramming on Open system design : hardware, software and applications: hardware, software and applications
Condition graphs for high-quality behavioral synthesis
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
HDL optimization using timed decision tables
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Behavior tables: a basis for system representation and transformational system synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Decomposition of timed decision tables and its use in presynthesis optimizations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Bridge: a versatile behavioral synthesis system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Timed decision tables: A model for embedded system representation and optimization
Timed decision tables: A model for embedded system representation and optimization
HardwareC -- A Language for Hardware Design (Version 2.0)
HardwareC -- A Language for Hardware Design (Version 2.0)
False path analysis based on hierarchical control representation
Proceedings of the 11th international symposium on System synthesis
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Execution condition analysis in high level synthesis: a unified approach
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A global approach to improve conditional hardware reuse in high-level synthesis
Journal of Systems Architecture: the EUROMICRO Journal
Constraints-driven scheduling and resource assignment
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Equivalence checking of arithmetic expressions using fast evaluation
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Expression equivalence checking using interval analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
Scheduling and binding are two major tasks in architectural synthesis from behavioral descriptions. The information about the mutually exclusive pairs of operations is very useful in reducing both the total delay of the schedule and the resource usage in the final circuit implementation. In this paper, we present an algorithm to identify the largest set of mutually exclusive operation pairs in behavioral descriptions. Our algorithm uses data-flow analysis on a tabular model of system functionality, and is shown to work better than the existing methods for identifying mutually exclusive operations.Interconnect Tuning Strategies for High-Performance Ics83590471abs.htm _Andrew B. Kahng, Sudhakar Muddu, Egino Sarto and Rahul SharmaSilicon Graphics, Inc.Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of line thicknesses, widths and spacings in multi-layer interconnect to simultaneously optimize signal distribution, signal performance, signal integrity, and interconnect manufacturability and reliability. This is a key activity in most leading-edge design projects, but has received little attention in the literature. Our work provides the first technology-specific studies of interconnect tuning in the literature. We center on global wiring layers and interconnect tuning issues related to bus routing, repeater insertion, and choice of shielding/spacing rules for signal integrity and performance. We ad-dress four basic questions. (1) How should width and spacing be allocated to maximize performance for a given line pitch? (2) For a given line pitch, what criteria affect the optimal interval at which repeaters should be inserted into global interconnects? (3) Under what circumstances are shield wires the optimum technique for improving interconnect performance? (4) In global interconnect with repeaters, what other interconnect tuning is possible? Our study of question (4) demonstrates a new approach of offsetting repeater placements that can reduce worst-case cross-chip delays by over 30% in current technologies.