Execution condition analysis in high level synthesis: a unified approach

Authors:
O. Peñalba;J. M. Mendías;M. C. Molina
Affiliations:
Departamento de Arquitectura de Computadores y Automdáica, Universidad Complutense de Madrid, Ciudad Universitaria s/n, 28040 Madrid, Spain, olgape@dacya.ucm.es;Departamento de Arquitectura de Computadores y Automdáica, Universidad Complutense de Madrid, Ciudad Universitaria s/n, 28040 Madrid, Spain, mendias@dacya.ucm.es;Departamento de Arquitectura de Computadores y Automdáica, Universidad Complutense de Madrid, Ciudad Universitaria s/n, 28040 Madrid, Spain, cmolinap@dacya.ucm.es
Venue:
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Year:
2000

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Abstract

The degree of conditional hardware reuse achieved after a high-level synthesis process depends on two factors: the number of mutually exclusive (m.e.) operations pairs that an algorithm can detect and the description style used by the designer when specifying the system. In this paper, we propose a method that deals with both aspects. It includes a mechanism to analyze the input description and identify all the m.e. operations pairs in a simple and homogeneous way, independently of the conditional constructs (IF or CASE) used to specify the control flow of the system. It also provides a collection of formal transformations on the input description which produces a specification of the same behavior that leads to an improved implementation --- in terms of the degree of conditional reuse that is achieved.