ISSS '00 Proceedings of the 13th international symposium on System synthesis
Execution condition analysis in high level synthesis: a unified approach
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A global approach to improve conditional hardware reuse in high-level synthesis
Journal of Systems Architecture: the EUROMICRO Journal
Co-simulation of Hybrid Systems: Signal-Simulink
FTRTFT '00 Proceedings of the 6th International Symposium on Formal Techniques in Real-Time and Fault-Tolerant Systems
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Identifying operation mutual exclusiveness is important in order to improve the quality of high-level synthesis results, by reducing either the required number of control steps or the needed hardware resources by conditional resource sharing. To this end we propose the Hierarchical Conditional Dependency Graph representation and an algorithm for identification of mutually exclusive operations. A hierarchical control organization permits to minimize the number of pair-wise exclusiveness tests during the identification process. Using graph transformations and reasoning on arithmetic inequalities, the proposed approach can produce results independent of description styles and identify more mutually exclusive operation pairs than previous approaches.