Formal Synthesis in Circuit Design - A Classification and Survey
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Execution condition analysis in high level synthesis: a unified approach
ISSS '00 Proceedings of the 13th international symposium on System synthesis
A global approach to improve conditional hardware reuse in high-level synthesis
Journal of Systems Architecture: the EUROMICRO Journal
Transformation of Equational Specification by Means of Genetic Programming
EuroGP '02 Proceedings of the 5th European Conference on Genetic Programming
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This paper presents a formal synthesis system which delegates the design space exploration to non-formal, and perhaps incorrect, high level synthesis tools. With a quadratic complexity, our system obtains either a truly correct-by-construction design, since the formal design process constitutes itself the verification process, or demonstrates that the solution found by the conventional tool was incorrect.