An efficient representation for formal synthesis
ISSS '97 Proceedings of the 10th international symposium on System synthesis
Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Correct high-level synthesis: a formal perspective
Proceedings of the conference on Design, automation and test in Europe
Combined Formal Post- and Presynthesis Verification in High Level Synthesis
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Formal Synthesis at the Algorithmic Level
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Visualizing System Factorizations with Behavior Tables
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
A constructive approach towards correctness of synthesis-application within retiming
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis
Proceedings of the 41st annual Design Automation Conference
Formalization of data flow computing and a coinductive approach to verifying flowware synthesis
Transactions on computational science I
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