Formulation and evaluation of scheduling techniques for control flow graphs
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Equivalence checking using cuts and heaps
DAC '97 Proceedings of the 34th annual Design Automation Conference
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Sequential equivalence checking without state space traversal
Proceedings of the conference on Design, automation and test in Europe
Formal Synthesis in Circuit Design - A Classification and Survey
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Inverting the Abstraction Mapping: A Methodology for Hardware Verification
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
Automatic verification of Pipelined Microprocessor Control
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
ICCD '98 Proceedings of the International Conference on Computer Design
Verification of synthesized circuits at register transfer level with flow graphs
EURO-DAC '91 Proceedings of the conference on European design automation
On the verification of synthesized designs using automatically generated transformational witnesses
Proceedings of the conference on Design, automation and test in Europe
Verification of Basic Block Schedules Using RTL Transformations
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis
Proceedings of the 41st annual Design Automation Conference
A Formal Verification Method of Scheduling in High-level Synthesis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Hand-in-hand verification of high-level synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Validating High-Level Synthesis
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Translation validation of high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalence checking of scheduling with speculative code transformations in high-level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Formal verification of code motion techniques using data-flow-driven equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Translation validation of scheduling in high level synthesis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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