Some Inference Rules for Integer Arithmetic for Verification of Flowchart Programs on Integers
IEEE Transactions on Software Engineering
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
An axiomatic basis for computer programming
Communications of the ACM
Introduction to High-Level Synthesis
IEEE Design & Test
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A Genetic Algorithm for the Synthesis of Structured Data Paths
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
A Formal Verification Method of Scheduling in High-level Synthesis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Using global code motions to improve the quality of results for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
| Hi-index | 0.00 |
This paper describes a formal verification methodology of high-level synthesis (HLS) process. The abstraction level of the input to HLS is so high compared to thatof the output that the verification has to proceed hand-in-hand with the synthesis process. The HLS verificationis performed in three phases in this work. The verification method is based on equivalence checking of two finite state machines with data-paths(FSMDs). Unlike most reported works that targets the individual phases independently, the proposed method applies to all these three phases. The method is strong enoughto accommodate control structure modification of the original behaviour, application of several code motion techniques during scheduling and register optimization during register allocation. It can also verify the correctness of the controller. A hand-in-hand synthesis and verification tool SAST has been developed and tested for effectiveness on several HLS benchmark circuits.