A Formal Verification Method of Scheduling in High-level Synthesis

Authors:
C Karfa;C Mandal;D Sarkar;S R. Pentakota;Chris Reade
Affiliations:
Indian Institute of Technology, Kharagpur, India;Indian Institute of Technology, Kharagpur, India;Indian Institute of Technology, Kharagpur, India;Indian Institute of Technology, Kharagpur, India;-
Venue:
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Year:
2006

Citing 9
Cited 8

Some Inference Rules for Integer Arithmetic for Verification of Flowchart Programs on Integers

IEEE Transactions on Software Engineering
Empirical evaluation of some high-level synthesis scheduling heuristics

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design

High-level synthesis: introduction to chip and system design
Formulation and evaluation of scheduling techniques for control flow graphs

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Automatic verification of scheduling results in high-level synthesis

DATE '99 Proceedings of the conference on Design, automation and test in Europe
An axiomatic basis for computer programming

Communications of the ACM
Introduction to Mathematical Theory of Computation

Introduction to Mathematical Theory of Computation
Introduction to High-Level Synthesis

IEEE Design & Test
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)

ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design

Hand-in-hand verification of high-level synthesis

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Verification method of dataflow algorithms in high-level synthesis

Journal of Systems and Software
Equivalence checking in C-based system-level design by sequentializing concurrent behaviors

ACST'07 Proceedings of the third conference on IASTED International Conference: Advances in Computer Science and Technology
Validating High-Level Synthesis

CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Automatic merge-point detection for sequential equivalence checking of system-level and RTL descriptions

ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Formal verification with Isabelle/HOL in practice: finding a bug in the GCC scheduler

FMICS'07 Proceedings of the 12th international conference on Formal methods for industrial critical systems
Translation validation of high-level synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a formal method for checking the equivalence between the finite state machine with data path (FSMD) model of the high-level behavioural specification and the FSMD model of the behaviour transformed by the scheduler. The method consists in introducing cutpoints in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints and finally, identifying equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs interchanged. The method is strong enough to accommodate merging of the segments in the original behaviour by the typical scheduler such as DLS, a feature very common in scheduling but not captured by many works reported in the literature. It also handles arithmetic transformations.