Equivalence checking in C-based system-level design by sequentializing concurrent behaviors

  • Authors:

  • Thanyapat Sakunkonchak;Takeshi Matsumoto;Hiroshi Saito;Satoshi Komatsu;Masahiro Fujita

  • Affiliations:

  • VLSI Design and Education Center, University of Tokyo, Tokyo, Japan;Dept. of Electronics Engineering, University of Tokyo, Tokyo, Japan;Dept. of Computer Hardware, University of Aizu, Aziu-Wakamatsu, Japan;VLSI Design and Education Center, University of Tokyo, Tokyo, Japan;VLSI Design and Education Center, University of Tokyo, Tokyo, Japan

  • Venue:
  • ACST'07 Proceedings of the third conference on IASTED International Conference: Advances in Computer Science and Technology
  • Year:
  • 2007

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Abstract

In system-level designs, since many incremental refinements are applied to the designs, equivalence checking between each refinement should be applied. However, proving whether two concurrent designs are equivalent is a difficult task, not to mention that the concurrent design itself can be error-prone. In this paper, we propose an equivalence checking method for C-based descriptions of system-level designs by sequentializing the concurrent behaviors. Before sequentializing concurrent behaviors, we need to check that the design must not contain neither deadlock nor race condition. After the sequentialization, equivalence checking is performed by symbolic simulation. To show that our methodology can be applied to practical designs, we experiment with some SpecC designs developed by University of California Irvine (UCI). The results show that the proposed method is promising. Although the size of some designs are large, with heuristic search for concurrency and synchronization, the size of designs are reduced accordingly and hence we can perform equivalence checking with the sequentialized ones.