Verification of Basic Block Schedules Using RTL Transformations
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Equivalence checking in C-based system-level design by sequentializing concurrent behaviors
ACST'07 Proceedings of the third conference on IASTED International Conference: Advances in Computer Science and Technology
Translation validation of high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
Recent advances in system design are presented. The shift towards flexible hardware architectures that can support a variety of applications via programmability and reconfigurability is underlined. Essential to this process is the definition and use ...