Communicating sequential processes
Communicating sequential processes
Software pipelining: an effective scheduling technique for VLIW machines
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Parallel program design: a foundation
Parallel program design: a foundation
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic verification of scheduling results in high-level synthesis
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Translation validation for an optimizing compiler
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Automatic predicate abstraction of C programs
Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Proving correctness of compiler optimizations by temporal logic
POPL '02 Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Extended static checking for Java
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
System Design with SystemC
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Formal Methods in System Design
Automatic Extraction of Functional Parallelism from Ordinary Programs
IEEE Transactions on Parallel and Distributed Systems
TACAS '98 Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
TACAS '95 Proceedings of the First International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Using a PVS Embedding of CSP to Verify Authentication Protocols
TPHOLs '97 Proceedings of the 10th International Conference on Theorem Proving in Higher Order Logics
A Corrected Failure Divergence Model for CSP in Isabelle/HOL
FME '97 Proceedings of the 4th International Symposium of Formal Methods Europe on Industrial Applications and Strengthened Foundations of Formal Methods
Construction of Abstract State Graphs with PVS
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Ten Years of Partial Order Reduction
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
PVS: Combining Specification, Proof Checking, and Model Checking
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
CADE-17 Proceedings of the 17th International Conference on Automated Deduction
Handbook of automated reasoning
Handbook of automated reasoning
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Simple relational correctness proofs for static analyses and program transformations
Proceedings of the 31st ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Modular Verification of Software Components in C
IEEE Transactions on Software Engineering
Simplify: a theorem prover for program checking
Journal of the ACM (JACM)
Translation and Run-Time Validation of Loop Transformations
Formal Methods in System Design
A Formal Verification Method of Scheduling in High-level Synthesis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Automated refinement checking of concurrent systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Automated formal verification of scheduling with speculative code motions
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Into the Loops: Practical Issues in Translation Validation for Optimizing Compilers
Electronic Notes in Theoretical Computer Science (ENTCS)
A generic theorem prover of CSP refinement
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
A framework for comparing models of computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System modeling and transformational design refinement in ForSyDe [formal system design]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal verification of code motion techniques using data-flow-driven equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Translation validation for a verified OS kernel
Proceedings of the 34th ACM SIGPLAN conference on Programming language design and implementation
Translation validation of scheduling in high level synthesis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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The growing complexity of systems and their implementation into silicon encourages designers to look for ways to model designs at higher levels of abstraction and then incrementally build portions of these designs--automatically or manually--from these high-level specifications. Unfortunately, this translation process itself can be buggy, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. Therefore, checking if the implementation is a refinement or equivalent to its initial specification is of tremendous value. In this paper, we present an approach to automatically validate the implementation against its initial high-level specification using insights from translation validation, automated theorem proving, and relational approaches to reasoning about programs. In our experiments, we first focus on concurrent systems modeled as communicating sequential processes and show that their refinements can be validated using our approach. Next, we have applied our validation approach to a realistic scenario--a parallelizing high-level synthesis framework called Spark. We present the details of our algorithm and experimental results.