Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Global scheduling independent of control dependencies based on condition vectors
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
An efficient resource-constrained global scheduling technique for superscalar and VLIW processors
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
Global scheduling with code-motions for high-level synthesis applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new framework for exhaustive and incremental data flow analysis using DJ graphs
PLDI '96 Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Advanced compiler design and implementation
Advanced compiler design and implementation
A reordering technique for efficient code motion
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Speculation techniques for high level synthesis of control intensive designs
Proceedings of the 38th annual Design Automation Conference
Conditional speculation and its effects on performance and area for high-level snthesis
Proceedings of the 14th international symposium on Systems synthesis
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Dynamic common sub-expression elimination during scheduling in high-level synthesis
Proceedings of the 15th international symposium on System Synthesis
Automatic Extraction of Functional Parallelism from Ordinary Programs
IEEE Transactions on Parallel and Distributed Systems
Trailblazing: A Hierarchical Approach to Percolation Scheduling
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 02
Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
A new symbolic technique for control-dependent scheduling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Modular scheduling of guarded atomic actions
Proceedings of the 41st annual Design Automation Conference
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Customisable Hardware Compilation
The Journal of Supercomputing
Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Extracting Speedup From C-Code With Poor Instruction-Level Parallelism
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 14 - Volume 15
Automatic generation of application-specific systems based on a micro-programmed Java core
Proceedings of the 2005 ACM symposium on Applied computing
Developing critical systems with PLD components
Proceedings of the 10th international workshop on Formal methods for industrial critical systems
Novel architecture for loop acceleration: a case study
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Worst case execution time analysis for synthesized hardware
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A methodology to implement real-time applications onto reconfigurable circuits
The Journal of Supercomputing
Resource sharing in pipelined CDFG synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Hardware synthesis from guarded atomic actions with performance specifications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Scheduling under resource constraints using dis-equations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Software thread integration for embedded system display applications
ACM Transactions on Embedded Computing Systems (TECS)
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
An automated, FPGA-based reconfigurable, low-power RFID tag
Microprocessors & Microsystems
A code refinement methodology for performance-improved synthesis from C
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A consistent design methodology for wireless embedded systems
EURASIP Journal on Applied Signal Processing
Efficient design methods for embedded communication systems
EURASIP Journal on Embedded Systems
EURASIP Journal on Applied Signal Processing
Thread warping: a framework for dynamic synthesis of thread accelerators
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
SoCDAL: System-on-chip design AcceLerator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
C is for circuits: capturing FPGA circuits as sequential code for portability
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Achieving programming model abstractions for reconfigurable computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
ARISE Machines: Extending Processors with Hybrid Accelerators
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Validating High-Level Synthesis
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Optimus: efficient realization of streaming applications on FPGAs
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
A holistic approach for tightly coupled reconfigurable parallel processors
Microprocessors & Microsystems
A compiler intermediate representation for reconfigurable fabrics
International Journal of Parallel Programming
Parallelization Approaches for Hardware Accelerators --- Loop Unrolling Versus Loop Partitioning
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
An Application Development Framework for ARISE Reconfigurable Processors
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Building heterogeneous reconfigurable systems with a hardware microkernel
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Designing hardware with dynamic memory abstraction
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Optimized generation of memory structure in compiling window operations onto reconfigurable hardware
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
ColSpace: towards algorithm/implementation co-optimization
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Data path refinement algorithm in high-level synthesis based on dynamic programming
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Translation validation of high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 47th Design Automation Conference
Finding the best compromise in compiling compound loops to Verilog
Journal of Systems Architecture: the EUROMICRO Journal
Automated synthesis of streaming C applications to process networks in hardware
Proceedings of the Conference on Design, Automation and Test in Europe
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Impact of high-level transformations within the ROCCC framework
ACM Transactions on Architecture and Code Optimization (TACO)
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic generation of fpga-specific pipelined accelerators
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The ARISE approach for extending embedded processors with arbitrary hardware accelerators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
Building multimedia security applications in the MPEG reconfigurable video coding (RVC) framework
Proceedings of the thirteenth ACM multimedia workshop on Multimedia and security
A design methodology to implement memory accesses in high-level synthesis
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An energy and power-aware approach to high-level synthesis of asynchronous systems
Proceedings of the International Conference on Computer-Aided Design
ESL Design and Verification: A Prescription for Electronic System Level Methodology
ESL Design and Verification: A Prescription for Electronic System Level Methodology
Divide and conquer high-level synthesis design space exploration
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Formal verification of code motion techniques using data-flow-driven equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
High-level synthesis: productivity, performance, and software constraints
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Journal of Systems Architecture: the EUROMICRO Journal
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
Elastic computing: A portable optimization framework for hybrid computers
Parallel Computing
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Scalable communication architectures for massively parallel hardware multi-processors
Journal of Parallel and Distributed Computing
FPGA-specific synthesis of loop-nests with pipelined computational cores
Microprocessors & Microsystems
Quipu: A Statistical Model for Predicting Hardware Resources
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Translation validation of scheduling in high level synthesis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications
Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting area/delay tradeoffs in high-level synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Compiling for power with ScalaPipe
Journal of Systems Architecture: the EUROMICRO Journal
Fast and effective placement and routing directed high-level synthesis for FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Secure computing with the MPEG RVC framework
Image Communication
Design of massively parallel hardware multi-processors for highly-demanding embedded applications
Microprocessors & Microsystems
Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints
Journal of Systems Architecture: the EUROMICRO Journal
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This paper presents a modular and extensible high-levelsynthesis research system, called SPARK, that takes a behavioral description in ANSI-C as input and produces synthesizable register-transfer level VHDL. SPARK uses parallelizing compiler technology developed previously to enhance instruction-level parallelism and re-instruments it forhigh-level synthesis by incorporating ideas of mutual exclusivity of operations, resource sharing and hardware costmodels. In this paper, we present the design flow throughthe SPARK system, a set of transformations that includespeculative code motions and dynamic transformations andshow how these transformations and other optimizing synthesis and compiler techniques are employed by a scheduling heuristic. Experiments are performed on two moderately complex industrial applications, namely, MPEG-1 andthe GIMP image processing tool.The results show that thevarious code transformations lead to up to 70% improvements in performance without any increase in the overallarea and critical path of the final synthesized design.