Deterministic Processor Scheduling
ACM Computing Surveys (CSUR)
The Organization of Microprogram Stores
ACM Computing Surveys (CSUR)
Local Microcode Compaction Techniques
ACM Computing Surveys (CSUR)
A comparison of list schedules for parallel processing systems
Communications of the ACM
Flow Analysis of Computer Programs
Flow Analysis of Computer Programs
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Global optimization of microprograms through modular control constructs
MICRO 12 Proceedings of the 12th annual workshop on Microprogramming
Methods of compacting microprograms
Methods of compacting microprograms
The Inhibition of Potential Parallelism by Conditional Jumps
IEEE Transactions on Computers
Percolation of Code to Enhance Parallel Dispatching and Execution
IEEE Transactions on Computers
Instruction scheduling for the IBM RISC System/6000 processor
IBM Journal of Research and Development
OHMEGA: a VLSI superscalar processor architecture for numerical applications
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Software pipelining: an evaluation of enhanced pipelining
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Instruction scheduling in the TOBEY compiler
IBM Journal of Research and Development
Profile-driven instruction level parallel scheduling with application to super blocks
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Software pipelining loops with conditional branches
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Wavefront scheduling: path based data representation and scheduling of subgraphs
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Compiler optimization of dynamic data distributions for distributed-memory multicomputers
Compiler optimizations for scalable parallel systems
Modeling the impact of run-time uncertainty on optimal computation scheduling using feedback
ICPP '97 Proceedings of the international Conference on Parallel Processing
Copy Elimination for Parallelizing Compilers
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
A Spill Code Placement Framework for Code Scheduling
LCPC '98 Proceedings of the 11th International Workshop on Languages and Compilers for Parallel Computing
Compile-Time Based Performance Prediction
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Instruction Scheduling in the Presence of Java's Runtime Exceptions
LCPC '99 Proceedings of the 12th International Workshop on Languages and Compilers for Parallel Computing
Load Scheduling with Profile Information
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Branch Prediction Using Profile Data
Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
PROPAN: A Retargetable System for Postpass Optimisations and Analyses
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Performance Issues in Parallel Processing Systems
Performance Evaluation: Origins and Directions
Alias Analysis by Means of a Model Checker
CC '01 Proceedings of the 10th International Conference on Compiler Construction
A Novel Probabilistic Data Flow Framework
CC '01 Proceedings of the 10th International Conference on Compiler Construction
Comparing Tail Duplication with Compensation Code in Single Path Global Instruction Scheduling
CC '01 Proceedings of the 10th International Conference on Compiler Construction
An Architectural Overview of the Programmable Multimedia Processor, TM-1
COMPCON '96 Proceedings of the 41st IEEE International Computer Conference
Inter-Cluster Communication Models for Clustered VLIW Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Dynamic Optimization of Micro-Operations
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Memory Hierarchy Design for Jetpipeline: To Execute Scalar and Vector Instructions in Parallel
PAS '97 Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An Enhanced Co-Scheduling Method using Reduced MS-State Diagrams
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
A resource request model for microcode compaction
ACM SIGMICRO Newsletter
An Analytical Approach to Scheduling Code for Superscalar and VLIW Architectures
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
Partitioning of Variables for Multiple-Register-File VLIW Architectures
ICPP '94 Proceedings of the 1994 International Conference on Parallel Processing - Volume 01
A backtracking instruction scheduler using predicate-based code hoisting to fill delay slots
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
The potential of trace-level parallelism in Java programs
Proceedings of the 5th international symposium on Principles and practice of programming in Java
Experiments in Automatic Microcode Generation
IEEE Transactions on Computers
Global Compaction of Horizontal Microprograms Based on the Generalized Data Dependency Graph
IEEE Transactions on Computers
Measuring the Parallelism Available for Very Long Instruction Word Architectures
IEEE Transactions on Computers
A Preliminary Evaluation of Trace Scheduling for Global Microcode Compaction
IEEE Transactions on Computers
Fault-safe code motion for type-safe languages
Proceedings of the 6th annual IEEE/ACM international symposium on Code generation and optimization
Proceedings of the 2008 ACM symposium on Applied computing
Compiler and hardware support for reducing the synchronization of speculative threads
ACM Transactions on Architecture and Code Optimization (TACO)
On the exploitation of loop-level parallelism in embedded applications
ACM Transactions on Embedded Computing Systems (TECS)
Optimal trace scheduling using enumeration
ACM Transactions on Architecture and Code Optimization (TACO)
Microcode compaction: looking backward and looking forward
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
Techniques for efficient placement of synchronization primitives
Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming
Convergent Compilation Applied to Loop Unrolling
Transactions on High-Performance Embedded Architectures and Compilers I
A study of potential parallelism among traces in Java programs
Science of Computer Programming
Temporal instruction fetch streaming
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
An 8-bit systolic AES architecture for moderate data rate applications
Microprocessors & Microsystems
Mostly static program partitioning of binary executables
ACM Transactions on Programming Languages and Systems (TOPLAS)
Synchronization optimizations for efficient execution on multi-cores
Proceedings of the 23rd international conference on Supercomputing
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Hybrid multithreading for VLIW processors
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
The instruction register file micro-architecture
Future Generation Computer Systems - Special issue: Parallel computing technologies
A real system evaluation of hardware atomicity for software speculation
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
International Journal of Modelling and Simulation
Paper: A boltzmann machine approach to code optimization
Parallel Computing
The interprocedural express-lane transformation
CC'03 Proceedings of the 12th international conference on Compiler construction
Tree traversal scheduling: a global instruction scheduling technique for VLIW/EPIC processors
LCPC'01 Proceedings of the 14th international conference on Languages and compilers for parallel computing
An adaptive strategy for inline substitution
CC'08/ETAPS'08 Proceedings of the Joint European Conferences on Theory and Practice of Software 17th international conference on Compiler construction
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
Instruction scheduling for VLIW processors under variation scenario
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Compilers, architectures and synthesis for embedded computing: retrospect and prospect
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Dynamic elimination of overflow tests in a trace compiler
CC'11/ETAPS'11 Proceedings of the 20th international conference on Compiler construction: part of the joint European conferences on theory and practice of software
Static speculation as post-link optimization for the Grid Alu processor
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
Trace-Based data cache leakage reduction at link time
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Hardware support for multithreaded execution of loops with limited parallelism
PCI'05 Proceedings of the 10th Panhellenic conference on Advances in Informatics
Trace-Based runtime instruction rescheduling for architecture extension
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
An overview of the open research compiler
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
The use of traces for inlining in java programs
LCPC'04 Proceedings of the 17th international conference on Languages and Compilers for High Performance Computing
Selective runtime memory disambiguation in a dynamic binary translator
CC'06 Proceedings of the 15th international conference on Compiler Construction
Generating optimal contiguous evaluations for expression DAGs
Computer Languages
Scheduling expression DAGs for minimal register need
Computer Languages
Probabilistic symbolic execution
Proceedings of the 2012 International Symposium on Software Testing and Analysis
API compilation for image hardware accelerators
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Elimination of parallel copies using code motion on data dependence graphs
Computer Languages, Systems and Structures
LUCAS: latency-adaptive unified cluster assignment and instruction scheduling
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Ball-Larus path profiling across multiple loop iterations
Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications
Software thread integration for instruction-level parallelism
ACM Transactions on Embedded Computing Systems (TECS)
Vectorization past dependent branches through speculation
PACT '13 Proceedings of the 22nd international conference on Parallel architectures and compilation techniques
CAeSaR: unified cluster-assignment scheduling and communication reuse for clustered VLIW processors
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Microcode Compression Using Structured-Constrained Clustering
International Journal of Parallel Programming
| Hi-index | 15.00 |
Microcode compaction is the conversion of sequential microcode into efficient parallel (horizontal) microcode. Local compaction techniques are those whose domain is basic blocks of code, while global methods attack code with a general flow control. Compilation of high-level microcode languages into efficient horizontal microcode and good hand coding probably both require effective global compaction techniques.