Effective compiler support for predicated execution using the hyperblock
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The superblock: an effective technique for VLIW and superscalar compilation
The Journal of Supercomputing - Special issue on instruction-level parallelism
Advanced compiler design and implementation
Advanced compiler design and implementation
Introducing the IA-64 Architecture
IEEE Micro
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Adapting instruction level parallelism for optimizing leakage in VLIW architectures
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Characterization and modeling of run-time techniques for leakage power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Speed binning aware design methodology to improve profit under parameter variations
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Compiler-directed thermal management for VLIW functional units
Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Yield-Aware Cache Architectures
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Working with process variation aware caches
Proceedings of the conference on Design, automation and test in Europe
Trace Scheduling: A Technique for Global Microcode Compaction
IEEE Transactions on Computers
Temperature and Process Variations Aware Power Gating of Functional Units
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Power Reduction of Functional Units Considering Temperature and Process Variations
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Block remap with turnoff: a variation-tolerant cache design technique
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 5th conference on Computing frontiers
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Process variations in components like adders, multipliers, etc., of different Integer Functional Units (IFUs) in VLIW (Very Long InstructionWord) processors may cause these units to operate at various speeds, resulting in non-uniform latency IFUs. Worst-case techniques to deal with the non-uniform latency IFUs may incur significant performance and/or leakage energy loss. In this work, we propose two process variation-aware compiletime techniques to handle non-uniform latency IFUs. In the first technique, namely 'turn-off', we turn off all the process variation affected high latency IFUs. In the second technique, namely 'ondemand turn-on', we use some of the process variation affected high latency IFUs by turning them on whenever there is a requirement. Our experimental results show that with these techniques, the non-uniform latency IFU can be tackled without much performance penalty. The proposed techniques also achieve significant reduction in leakage energy consumption because of turning off of some of the IFUs.