Instruction scheduling for VLIW processors under variation scenario
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Proceedings of the International Conference on Computer-Aided Design
Static statistical MPSoC power optimization by variation-aware task and communication scheduling
Microprocessors & Microsystems
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Technology scaling has resulted in an exponential in- crease in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Integer ALUs are regions of high power density and significantly contribute to the variation in the whole pro- cessor power consumption. Hence, it is important to reduce both the power consumption and the variation in power consumption of the FUs. Among existing FU power re- duction techniques, power gating (PG) has been most ef- fective. In this paper, we introduce a leakage sensor inside the FUs and propose a temperature and process variation aware power gating scheme, Leakage Aware Power Gating (LA-PG). Our experimental results demonstrate that LA-PG results in 22% reduction in mean and a 25% reduction in standard deviation of the ALU energy consumption when compared to existing power gating techniques, without sig- nificant performance penalty.