Modeling and analysis of leakage power considering within-die process variations
Proceedings of the 2002 international symposium on Low power electronics and design
Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Considering process variations during system-level power analysis
Proceedings of the 2006 international symposium on Low power electronics and design
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Prediction of leakage power under process uncertainties
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Guaranteeing performance yield in high-level synthesis
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Variation-aware task allocation and scheduling for MPSoC
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A performance study of multiprocessor task scheduling algorithms
The Journal of Supercomputing
Temperature and Process Variations Aware Power Gating of Functional Units
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
A variation aware high level synthesis framework
Proceedings of the conference on Design, automation and test in Europe
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Variability-aware robust design space exploration of chip multiprocessor architectures
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing variation-aware high-level synthesis considering accurate yield computation
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
SRAM leakage reduction by row/column redundancy under random within-die delay variation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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Corner-case analysis is a well-known technique to cope with occasional deviations occurring during the manufacturing process of semiconductors. However, the increasing amount of process variation in nanometer technologies has made it inevitable to move toward statistical analysis methods, instead of deterministic worst-case-based techniques, at all design levels. We show that by statically considering statistical effects of random and systematic process variation on performance and power consumption of a Multiprocessor System-on-Chip (MPSoC), significant power improvement can be achieved by static software-level optimizations such as task and communication scheduling. Moreover, we analyze and show how the changes in the amount of process variability as well as values of other system constraints affect the achieved power improvement in such system-level optimizations. We employ a mixed-level model of MPSoC critical components so as to obtain the statistical distribution of frequency and power consumption of MPSoCs in presence of both within-die and die-to-die process variations. Using this model, we show that our proposed statistical task scheduling algorithm can achieve substantial power reduction under different values of system constraints. Furthermore, the effectiveness of our proposed statistical task scheduling approach will even increase with the increasing amount of process variation expected to occur in future technologies.