Yield-oriented evaluation methodology of network-on-chip routing implementations
SOC'09 Proceedings of the 11th international conference on System-on-chip
Improving the Performance of GALS-Based NoCs in the Presence of Process Variation
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A methodology for the characterization of process variation in NoC links
Proceedings of the Conference on Design, Automation and Test in Europe
Electromigration-aware dynamic routing algorithm for network-on-chip applications
International Journal of High Performance Systems Architecture
Characterizing the impact of process variation on 45 nm NoC-based CMPs
Journal of Parallel and Distributed Computing
Performance Analysis of On-Chip Communication Structures under Device Variability
International Journal of Embedded and Real-Time Communication Systems
International Journal of Embedded and Real-Time Communication Systems
Static statistical MPSoC power optimization by variation-aware task and communication scheduling
Microprocessors & Microsystems
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A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected through programmable crosspoints. Since an NoC may provide a number of paths between a given source and destination, manufacturing or runtime faults on one interconnect does not necessarily render the chip useless. It is partly because of this fault tolerance that NoCs have emerged as a viable alternative for implementing communication between functional units of a chip in the nanometer regime, where high defect rates are prevalent. In this paper, we quantify the fault tolerance offered by an NoC against process variations. Specifically, we develop an analytical model for the probability of failure in buffered global NoC links due to interconnect dishing, and effective channel length variation. Using the developed probability model, we study the impact of link failure on the number of cycles required to establish communications in NoC applications.