Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
From blind certainty to informed uncertainty
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Repeater Insertion To Minimise Delay In Coupled Interconnects
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Interconnect intellectual property for network-on-chip (NoC)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
SILENT: serialized low energy transmission coding for on-chip interconnection networks
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Impact of Variability on Clock Skew in H-tree Clock Networks
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Statistical Device Variability and its Impact on Yield and Performance
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Variability of flip-flop timing at sub-threshold voltages
Proceedings of the 13th international symposium on Low power electronics and design
Statistical interconnect metrics for physical-design optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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On-chip communication is becoming an important bottleneck in the design and operation of high performance systems where it has to face additional challenges due to device variability. Communication structures such as tapered buffer drivers, interconnects, repeaters, and data storage elements are vulnerable to variability, which can limit the performance of the on-chip communication networks. In this regard, it becomes important to have a complete understanding of the impact that variability will have on the performance of these circuit elements in order to design high yield and reliable systems. In this paper, the authors have characterized the performance of the communication structures under the impact of random dopant fluctuation RDF for the future technology generations of 25, 18, and 13 nm. For accurate characterization of their performance, a Monte Carlo simulation method has been used along with predictive device models for the given technologies. Analytical models have been developed for the link failure probability of a repeater inserted interconnect which uses characterization data of all communication structures to give an accurate prediction of the link failure probability. The model has also been extended to calculate the link failure probability of a wider communication link.