Proceedings of the 2008 international workshop on System level interconnect prediction
Impact of device variability in the communication structures for future synchronous SoC designs
SOC'09 Proceedings of the 11th international conference on System-on-chip
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
Performance Analysis of On-Chip Communication Structures under Device Variability
International Journal of Embedded and Real-Time Communication Systems
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Clock distribution networks play a key role in determining overall system performance. In this paper, we investigate the effect of parameter variations on the performance of a commonly used clock distribution structure, a H-tree clock network. The design of robust high performance clock networks face significant challenges due to increasing parameter variations in sub-65nm technologies. As shown in the results, the contribution of interconnect variations to clock skew has risen by upto 3 times from 180nm to 45nm technology. It also suggests that the effect of variability is most prominent at the second and third stages of the 5-stage H-tree clock network. This analysis will help develop mitigation techniques that focus on addressing specific failure mechanisms caused by variability in clock networks.