Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
Proceedings of the 41st annual Design Automation Conference
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Information Theoretic Capacity of Long On-chip Interconnects in the Presence of Crosstalk
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Design and Analysis of Experiments
Design and Analysis of Experiments
Worst-case delay analysis considering the variability of transistors and interconnects
Proceedings of the 2007 international symposium on Physical design
Impact of Variability on Clock Skew in H-tree Clock Networks
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Statistical interconnect metrics for physical-design optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With deep submicron technologies, the importance of interconnect parasitics on delay and noise has been an ever increasing trend. Consequently the variation in interconnect parameters have a larger impact on final timing and functional yield of the product. We present a comprehensive analysis to quantify the impact of parametric variations on the reliability of global interconnect links in the presence of crosstalk. The impact of parametric variations on wire delay and crosstalk noise is studied for a global interconnect structure in 90nm UMC technology, followed by a novel technique to estimate the bit error rate (BER) of such links. This methodology is employed to explore the design space of interconnect channels in order to mitigate the impact of variability.