Worst-case delay analysis considering the variability of transistors and interconnects

Authors:
Takayuki Fukuoka;Akira Tsuchiya;Hidetoshi Onodera
Affiliations:
Kyoto University, Kyoto, Japan;Kyoto University, Kyoto, Japan;Kyoto University, Kyoto, Japan
Venue:
Proceedings of the 2007 international symposium on Physical design
Year:
2007

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Abstract

This paper discusses the condition that gives the statistical worst-casedelay of a stage under the fluctuation of interconnect structure and transistor performance. The delay of a stage is a function of many parameters such as drive strength of the gate, interconnect length and interconnect structures (width, thickness, spacing, etc.), and therefore the condition for the worst-case delay also becomes a function of those parameters. We examine the worst-case condition using a simple equivalent circuit and show how the worst-case condition varies. It is shown that the worst-case condition of an interconnect structure for a certain range of interconnect length moves toward the best-case for other range of interconnect length, and hence it is important to locate the worst-case condition correctly for accurate estimation of the worst-case stage delay. We show a simple criteria for the direction of the worst-case condition of an interconnect structure.