Statistical corner conditions of interconnect delay (corner LPE specifications)

Authors:
Kenta Yamada;Noriaki Oda
Affiliations:
NEC Electronics Corporation, Shimonumabe, Nakahara-Ku, Kawasaki, Kanagawa, Japan;NEC Electronics Corporation, Shimonumabe, Nakahara-Ku, Kawasaki, Kanagawa, Japan
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

Citing 0
Cited 2

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Abstract

Timing closure in LSI design becomes more and more difficult. But the conventional interconnect RC extraction method have over-margins caused by its corner conditions settings. In this paper, statistical corner conditions using the independence of variations between process parameters and between interconnect layers are proposed. As a result, the fast-to-slow guardband decreases by half in average, compared to the conventional method. The proposed method is ready for implementation to LPE tools.