Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Variational delay metrics for interconnect timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
Physical CAD changes to incorporate design for lithography and manufacturability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Interval-valued reduced order statistical interconnect modeling
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case delay analysis considering the variability of transistors and interconnects
Proceedings of the 2007 international symposium on Physical design
Fast min-cost buffer insertion under process variations
Proceedings of the 44th annual Design Automation Conference
Multi-layer interconnect performance corners for variation-aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Interconnect performance corners considering crosstalk noise
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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This paper introduces a fast analytical model for determining accurate parasitic values for best- and worst-case delays of a stage under interconnect process variations. The inputs to the model are the nominal values for each interconnect and device parameter and the amount of variation in each interconnect parameter. The outputs of the model are the interconnect parameter dimensions within the range of process variation that yield the best- and worst-case delay of a stage. Simulations show that our model accurately predicts the performance corners of a stage while those predicted by traditional best/worst-case analysis methodologies can have an error of up to 28.42%.