Physical CAD changes to incorporate design for lithography and manufacturability

Authors:
Louis K. Scheffer
Affiliations:
Cadence Design Systems, Inc., San Jose, California
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

Citing 7
Cited 12

Subwavelength lithography and its potential impact on design and EDA

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Layout design methodolgies for sub-wavelength manufacturing

Proceedings of the 38th annual Design Automation Conference
Adoption of OPC and the impact on design and layout

Proceedings of the 38th annual Design Automation Conference
Advanced routing in changing technology landscape

Proceedings of the 2003 international symposium on Physical design
Performance-impact limited area fill synthesis

Proceedings of the 40th annual Design Automation Conference
TCAD development for lithography resolution enhancement

IBM Journal of Research and Development
Area fill synthesis for uniform layout density

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

RADAR: RET-aware detailed routing using fast lithography simulations

Proceedings of the 42nd annual Design Automation Conference
Post-routing redundant via insertion for yield/reliability improvement

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Maze routing with OPC consideration

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
CMP aware shuttle mask floorplanning

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Redundant-via enhanced maze routing for yield improvement

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Computation of accurate interconnect process parameter values for performance corners under process variations

Proceedings of the 43rd annual Design Automation Conference
Post-routing redundant via insertion and line end extension with via density consideration

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
High-performance routing at the nanometer scale

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Dead via minimization by simultaneous routing and redundant via insertion

Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Simultaneous redundant via insertion and line end extension for yield optimization

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Quantified Score

Hi-index	0.01

Visualization

Abstract

The next few process generations (65 nm and below) will have serious lithography and manufacturing constraints since the feature size is shrinking much more rapidly than the wavelengths used in manufacturing the chips. This paper starts with a quick tutorial on the Design for Manufacturability problems of these process generations, concentrating primarily on the limitations of optical lithography. The remainder of the talk covers the changes to physical design tools, such as placement and routing, that are needed to cope with these problems.